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? 2010 microchip technology inc. ds39975a pic24fj256gb210 family data sheet 64/100-pin, 16-bit flash microcontrollers with usb on-the-go (otg)
ds39975a-page 2 ? 2010 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-209-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2010 microchip technology inc. ds39975a-page 3 pic24fj256gb210 family universal serial bus features: ? usb v2.0 on-the-go (otg) compliant ? dual role capable ? can act as either host or peripheral ? low-speed (1.5 mbps) and full-speed (12 mbps) usb operation in host mode ? full-speed usb operation in device mode ? high-precision pll for usb ? supports up to 32 endpoints (16 bidirectional): - usb module can use the internal ram location from 0x800 to 0xffff as usb endpoint buffers ? on-chip usb transceiver with interface for off-chip transceiver ? supports control, interrupt, isochronous and bulk transfers ? on-chip pull-up and pull-down resistors peripheral features: ? enhanced parallel master port/parallel slave port (epmp/psp): - direct access from cpu with an extended data space (eds) interface - 4, 8 and 16-bit wide data bus - up to 23 programmable address lines - up to 2 chip select lines - up to 2 acknowledgement lines (one per chip select) - programmable address/data multiplexing - programmable address and data wait states - programmable polarity on control signals peripheral features (continued): ? peripheral pin select: - up to 44 available pins (100-pin devices) ? three 3-wire/4-wire spi modules (supports 4 frame modes) ?three i 2 c? modules supporting multi-master/slave modes and 7-bit/10-bit addressing ?four uart modules: - supports rs-485, rs-232, lin/j2602 protocols and irda ? ? five 16-bit timers/counters with programmable prescaler ? nine 16-bit capture inputs, each with a dedicated time base ? nine 16-bit compare/pwm outputs, each with a dedi- cated time base ? hardware real-time clock and calendar (rtcc) ? enhanced programmable cyclic redundancy check (crc) generator ? up to 5 external interrupt sources pic24fj device pins program memory (bytes) sram (bytes) remappable peripherals i 2 c? 10-bit a/d (ch) comparators ctmu epmp/psp rtcc usb otg remappable pins 16-bit timers ic/oc pwm uart w/irda ? spi pic24fj128gb206 64 128k 96k 29 5 9/9 4 3 3 16 3 y y y y pic24fj256gb206 64 256k 96k 29 5 9/9 4 3 3 16 3 y y y y PIC24FJ128GB210 100/121 128k 96k 44 5 9/9 4 3 3 24 3 y y y y pic24fj256gb210 100/121 256k 96k 44 5 9/9 4 3 3 24 3 y y y y 64/100-pin, 16-bit flas h microcontrollers with usb on-the-go (otg)
pic24fj256gb210 family ds39975a-page 4 ? 2010 microchip technology inc. high-performance cpu ? modified harvard architecture ? up to 16 mips operation at 32 mhz ? 8 mhz internal oscillator ? 17-bit x 17-bit single-cycle hardware multiplier ? 32-bit by 16-bit hardware divider ? 16 x 16-bit working register array ? c compiler optimized instruction set architecture with flexible addressing modes ? linear program memory addressing, up to 12 mbytes ? data memory addressing, up to 16 mbytes: - 2k sfr space - 30k linear data memory - 66k extended data memory - remaining (from 16 mbytes) memory (external) can be accessed using extended data memory ( eds) and epmp (eds is divided into 32-kbyte pages) ? two address generation units for separate read and write addressing of data memory power management: ? on-chip voltage regulator of 1.8v ? switch between clock sources in real time ? idle, sleep and doze modes with fast wake-up and two-speed start-up ? run mode: 800 ? a/mips, 3.3v typical ? sleep mode current down to 20 ? a, 3.3v typical ? standby current with 32 khz oscillator: 22 ? a, 3.3v typical analog features: ? 10-bit, up to 24-channel analog-to-digital (a/d) converter at 500 ksps: - operation is possible in sleep mode - band gap reference input feature ? three analog comparators with programmable input/output configuration ? charge time measurement unit (ctmu): - supports capacitive touch sensing for touch screens and capacitive switches - minimum time measurement setting at 100 ps ? available lvd interrupt v lvd level special microcontroller features: ? operating voltage range of 2.2v to 3.6v ? 5.5v tolerant input (digital pins only) ? configurable open-drain outputs on digital i/o ports ? high-current sink/source (18 ma/18 ma) on all i/o ports ? selectable power management modes: - sleep, idle and doze modes with fast wake-up ? fail-safe clock monitor (fscm) operation: - detects clock failure and switches to on-chip, frc oscillator ? on-chip ldo regulator ? power-on reset (por) and oscillator start-up timer (ost) ? brown-out reset (bor) ? flexible watchdog timer (wdt) with on-chip low-power rc oscillator for reliable operation ? in-circuit serial programming? (icsp?) and in-circuit debug (icd) via 2 pins ? jtag boundary scan support ? flash program memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - selectable write protection boundary - self-reprogrammable under software control - write protection option for configuration words
? 2010 microchip technology inc. ds39975a-page 5 pic24fj256gb210 family pin diagram (64-pin tqfp/qfn) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 22 44 24 25 26 27 28 29 30 31 32 1 46 45 23 43 42 41 40 39 c3inb/cn15/rd6 rp20 /pmrd/cn14/rd5 rp25 /pmwr/cn13/rd4 rp22 /pmbe0/cn52/rd3 dph/ rp23 /pmack1/cn51/rd2 v cpcon / rp24 /v buschg /cn50/rd1 pmd4/cn62/re4 pmd3/cn61/re3 pmd2/cn60/re2 pmd1/cn59/re1 v busst /v cmpst 1/v busvld /cn68/rf0 v cap sosci/c3ind/cn1/rc13 dmh/ rp11 /int0/cn49/rd0 scl1/ rp3 /pma15/pmcs2/cn55/rd10 dpln/sda1/ rp4 /pma14/pmcs1/cn54/rd9 rtcc/dmln/ rp2 /cn53/rd8 rp12 /pmack2/cn56/rd11 osco/clko/cn22/rc15 osci/clki/cn23/rc12 v dd d+/cn83/rg2 v usb v bus /rf7 rp16 /usbid/cn71/rf3 d-/cn84/rg3 av dd an8/ rp8 /cn26/rb8 an9/ rp9 /pma7/cn27/rb9 tms/cv ref /an10/pma13/cn28/rb10 tdo/an11/pma12/cn29/rb11 v dd pgec2/an6/ rp6 /cn24/rb6 pged2/an7/ rp7 /rcv/cn25/rb7 scl2/ rp17 /pma8/cn18/rf5 sda2/ rp10 /pma9/cn17/rf4 pmd5/cn63/re5 scl3/pmd6/cn64/re6 sda3/pmd7/cn65/re7 c1ind/ rp21 /pma5/cn8/rg6 v dd pgec3/an5/c1ina/v buson / rp18 /cn7/rb5 pged3/an4/c1inb/usboen/ rp28 /cn6/rb4 an3/c2ina/vpio/cn5/rb3 an2/c2inb/vmio/ rp13 /cn4/rb2 c1inc/ rp26 /pma4/cn9/rg7 c2ind/ rp19 /pma3/cn10/rg8 pgec1/an1/v ref -/ rp1 /cn3/rb1 pged1/an0/v ref +/pma6/ rp0 /cn2/rb0 c2inc/ rp27 /pma2/cn11/rg9 mclr tck/an12/ctedg2/pma11/cn30/rb12 tdi/an13ctedg1/pma10/cn31/rb13 an14/ctpls/ rp14 /pma1/cn32/rb14 an15/ rp29 /refo/pma0/cn12/rb15 pmd0/cn58/re0 v cmpst 2/sessvld/cn69/rf1 c3ina/sessend/cn16/rd7 v ss (1) v ss (1) v ss (1) envreg 63 62 61 59 60 58 57 56 54 55 53 52 51 49 50 38 37 34 36 35 33 17 19 20 21 18 av ss 64 sosco/sclki/t1ck/c3inc/ rpi37 /cn0/ note 1: the back pad on qfn devices should be connected to v ss . legend: rpn and rpin represents remappable peripheral pins. shaded pins indicate pins that are tolerant to up to +5.5v. pic24fjxxxgb206 rc14
pic24fj256gb210 family ds39975a-page 6 ? 2010 microchip technology inc. table 1: complete pin function de scriptions for 64-pin devices pin function pin function 1 pmd5/cn63/re5 33 rp16 /usbid/cn71/rf3 2 scl3/pmd6/cn64/re6 34 v bus /rf7 3 sda3/pmd7/cn65/re7 35 v usb 4c1ind/ rp21 /pma5/cn8/rg6 36 d-/cn84/rg3 5c1inc/ rp26 /pma4/cn9/rg7 37 d+/cn83/rg2 6c2ind/ rp19 /pma3/cn10/rg8 38 v dd 7mclr 39 osci/clki/cn23/rc12 8c2inc/ rp27 /pma2/cn11/rg9 40 osco/clko/cn22/rc15 9v ss 41 v ss 10 v dd 42 rtcc/dmln/ rp2 /cn53/rd8 11 pgec3/an5/c1ina/v buson / rp18 /cn7/rb5 43 dpln/sda1/ rp4 /pmack2/cn54/rd9 12 pged3/an4/c1inb/usboen/ rp28 /cn6/rb4 44 scl1/ rp3 /pma15/pmcs2 (1) /cn55/rd10 13 an3/c2ina/vpio/cn5/rb3 45 rp12 /pma14/pmcs1 (1) /cn56/rd11 14 an2/c2inb/vmio/ rp13 /cn4/rb2 46 dmh/ rp11 /int0/cn49/rd0 15 pgec1/an1/v ref -/ rp1 /cn3/rb1 47 sosci/c3ind/cn1/rc13 16 pged1/an0/v ref +/pma6/ rp0 /cn2/rb0 48 sosco/sclki/t1ck/c3inc/ rpi37 /cn0/rc14 17 pgec2/an6/ rp6 /cn24/rb6 49 v cpcon / rp24 /v buschg /cn50/rd1 18 pged2/an7/ rp7 /rcv/cn25/rb7 50 dph/ rp23 /pmack1/cn51/rd2 19 av dd 51 rp22 /pmbe0/cn52/rd3 20 av ss 52 rp25 /pmwr/cn13/rd4 21 an8/ rp8 /cn26/rb8 53 rp20 /pmrd/cn14/rd5 22 an9/ rp9 /pma7/cn27/rb9 54 c3inb/cn15/rd6 23 tms/cv ref /an10/pma13/cn28/rb10 55 c3ina/sessend/cn16/rd7 24 tdo/an11/pma12/cn29/rb11 56 v cap 25 v ss 57 envreg 26 v dd 58 v busst /v cmpst 1/v busvld /cn68/rf0 27 tck/an12/ctedg2/pma11/cn30/rb12 59 v cmpst 2/sessvld/cn69/rf1 28 tdi/an13/ctedg1/pma10/cn31/rb13 60 pmd0/cn58/re0 29 an14/ctpls/ rp14 /pma1/cn32/rb14 61 pmd1/cn59/re1 30 an15/ rp29 /refo/pma0/cn12/rb15 62 pmd2/cn60/re2 31 sda2/ rp10 /pma9/cn17/rf4 63 pmd3/cn61/re3 32 scl2/ rp17 /pma8/cn18/rf5 64 pmd4/cn62/re4 legend: rpn and rpin represent remappable pins for peripheral pin select functions. note 1: pin assignment for pmcsx when csf<1:0> are not equal to ? 00 ?.
? 2010 microchip technology inc. ds39975a-page 7 pic24fj256gb210 family pin diagram (100-pin tqfp) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 100 rp20 /pmrd/cn14/rd5 rp25 /pmwr/cn13/rd4 pmd13/cn19/rd13 rpi42 /pmd12/cn57/rd12 rp22 /pmbe0/cn52/rd3 dph/ rp23 /pmack1/cn51/rd2 v cpcon / rp24 /v buschg /cn50/rd1 an22/pma17/cn40/ra7 an23/cn39/ra6 pmd2/cn60/re2 cn80/rg13 cn79/rg12 pma16/cn81/rg14 pmd1/cn59/re1 pmd0/cn58/re0 pmd8/cn77/rg0 pmd4/cn62/re4 pmd3/cn61/re3 v busst /v cmpst 1/v busvld /pmd11/cn68/rf0 v cap sosci/c3ind/cn1/rc13 dmh/ rp11 /int0/cn49/rd0 rp3 /pma15/pmcs2 / cn55/ dpln/ rp4 /pmack2/cn54/ dmln/rtcc/ rp2 /cn53/rd8 rp12/ pma14/pmcs1 / cn56/rd11 sda1/ rpi35 /pmbe1/cn44/ scl1/ rpi36 / osco/clko/cn22/rc15 osci/clki/cn23/rc12 v dd d+/cn83/rg2 v usb v bus /cn73/rf7 rp15 /cn74/rf8 d-/cn84/rg3 rp30 /cn70/rf2 rp16 /usbid/cn71/rf3 v ss v ref +/pma6/cn42/ra10 v ref -/pma7/cn41/ra9 av dd av ss an8/ rp8 /cn26/rb8 an9/ rp9 /cn27/rb9 an10/cv ref /pma13/cn28/rb10 an11/pma12/cn29/rb11 v dd rpi32 /pma18/pma5 / cn75/rf12 rp31 /cn76/rf13 v ss v dd rp5 /cn21/rd15 rpi43 /cn20/rd14 pgec2/an6/ rp6 /cn24/rb6 pged2/an7/ rp7 /rcv/cn25/rb7 rp17 /pma8/cn18/rf5 rp10 /pma9/cn17/rf4 pmd5/cn63/re5 scl3/pmd6/cn64/re6 sda3/pmd7/cn65/re7 rpi38 /cn45/rc1 rpi39 /cn46/rc2 rpi40 /cn47/rc3 an16/ rpi41 /pmcs2/pma22 / cn48/rc4 an17/c1ind/ rp21 /pma5/pma18 / cn8/ v dd tms/cn33/ra0 rpi33 /pmcs1/cn66/re8 an21/ rpi34 /pma19/cn67/re9 pgec3/an5/c1ina/v buson / rp18 /cn7/rb5 an3/c2ina/vpio/cn5/rb3 an2/c2inb/vmio/ rp13 /cn4/rb2 rg6 an19/c2ind/ rp19 /pma3/pma21 / cn10/rg8 pgec1/an1/v ref -/ rp1 /cn3/rb1 pged1/an0/v ref + /rp0 /cn2/rb0 cn82/rg15 v dd an20/c2inc/ rp27 /pma2/cn11/rg9 mclr an12/pma11/ctedg2/cn30/rb12 an13/pma10/ctedg1/cn31/rb13 an14/ctpls/ rp14 /pma1/cn32/rb14 an15/refo/ rp29 /pma0/cn12/rb15 pmd9/cn78/rg1 v cmpst 2/sessvld/pmd10/cn69/rf1 c3ina/sessend/pmd15/cn16/rd7 c3inb/pmd14/cn15/rd6 tdo/cn38/ra5 sda2/pma20/pma4 / cn36/ra3 scl2/cn35/ra2 v ss v ss v ss envreg tdi/pma21/pma3/cn37/ra4 tck/cn34/ra1 sosco/sclki/tick/c3inc/ pged3/an4/c1inb/usboen/ rp28 /cn6/rb4 legend: rpn and rpin represent remappable peripheral pins. shaded pins indicate pins that are tolerant to up to +5.5v. an18/c1inc/ rp26 /pma4/pma20 / cn9/rg7 cn43/ra14 pma22/pmcs2 / ra15 rd9 rpi37 /cn0/rc14 pic24fjxxxgb210 rd10
pic24fj256gb210 family ds39975a-page 8 ? 2010 microchip technology inc. table 2: complete pin function de scriptions for 100-pin devices pinfunctionpinfunction 1 cn82/rg15 41 an12/pma11/ctedg2/cn30/rb12 2v dd 42 an13/pma10/ctedg1/cn31/rb13 3 pmd5/cn63/re5 43 an14/ctpls/ rp14 /pma1/cn32/rb14 4 scl3/pmd6/cn64/re6 44 an15/refo/ rp29 /pma0/cn12/rb15 5 sda3/pmd7/cn65/re7 45 v ss 6 rpi38 /cn45/rc1 46 v dd 7 rpi39 /cn46/rc2 47 rpi43 /cn20/rd14 8 rpi40 /cn47/rc3 48 rp5 /cn21/rd15 9 an16/ rpi41 /pmcs2/pma22 (2) /cn48/rc4 49 rp10 /pma9/cn17/rf4 10 an17/c1ind/ rp21 /pma5/pma18 (2) /cn8/rg6 50 rp17 /pma8/cn18/rf5 11 an18/c1inc/ rp26 /pma4/pma20 (2) /cn9/rg7 51 rp16 /usbid/cn71/rf3 12 an19/c2ind/ rp19 /pma3/pma21 (2) /cn10/rg8 52 rp30 /cn70/rf2 13 mclr 53 rp15 /cn74/rf8 14 an20/c2inc/ rp27 /pma2/cn11/rg9 54 v bus /cn73/rf7 15 v ss 55 v usb 16 v dd 56 d-/cn84/rg3 17 tms/cn33/ra0 57 d+/cn83/rg2 18 rpi33 /pmcs1/cn66/re8 58 scl2/cn35/ra2 19 an21/ rpi34 /pma19/cn67/re9 59 sda2/pma20/pma4 (2) /cn36/ra3 20 pgec3/an5/c1ina/v buson / rp18 /cn7/rb5 60 tdi/pma21/pma3 (2) /cn37/ra4 21 pged3/an4/c1inb/usboen/ rp28 /cn6/rb4 61 tdo/cn38/ra5 22 an3/c2ina/vpio/cn5/rb3 62 v dd 23 an2/c2inb/vmio/ rp13 /cn4/rb2 63 osci/clki/cn23/rc12 24 pgec1/an1/v ref - (1) / rp1 /cn3/rb1 64 osco/clko/cn22/rc15 25 pged1/an0/v ref + (1) / rp0 /cn2/rb0 65 v ss 26 pgec2/an6/ rp6 /cn24/rb6 66 scl1/ rpi36 /pma22/pmcs2 (2) /cn43/ra14 27 pged2/an7/ rp7 /rcv/cn25/rb7 67 sda1/ rpi35 /pmbe1/cn44/ra15 28 v ref -/pma7/cn41/ra9 68 dmln/rtcc/ rp2 /cn53/rd8 29 v ref +/pma6/cn42/ra10 69 dpln/ rp4 /pmack2/cn54/rd9 30 av dd 70 rp3 /pma15/pmcs2 (3) /cn55/rd10 31 av ss 71 rp12 /pma14/pmcs1 (3) /cn56/rd11 32 an8/ rp8 /cn26/rb8 72 dmh/ rp11 /int0/cn49/rd0 33 an9/ rp9 /cn27/rb9 73 sosci/c3ind/cn1/rc13 34 an10/cv ref /pma13/cn28/rb10 74 sosco/sclki/t1ck/c3inc/ rpi37 /cn0/rc14 35 an11/pma12/cn29/rb11 75 v ss 36 v ss 76 v cpcon / rp24 /v buschg /cn50/rd1 37 v dd 77 dph/ rp23 /pmack1/cn51/rd2 38 tck/cn34/ra1 78 rp22 /pmbe0/cn52/rd3 39 rp31 /cn76/rf13 79 rpi42 /pmd12/cn57/rd12 40 rpi32 /pma18/pma5 (2) /cn75/rf12 80 pmd13/cn19/rd13 legend: rpn and rpin represent remappable pins for peripheral pin select (pps) functions. note 1: alternate pin assignments for v ref + and v ref - when the altvref configuration bit is programmed. 2: alternate pin assignments for epmp when the altpmp configuration bit is programmed (only in 100-pin devices). 3: pin assignment for pmcsx when csf<1:0> is not equal to ? 00 ?.
? 2010 microchip technology inc. ds39975a-page 9 pic24fj256gb210 family 81 rp25 /pmwr/cn13/rd4 91 an23/cn39/ra6 82 rp20 /pmrd/cn14/rd5 92 an22/pma17/cn40/ra7 83 c3inb/pmd14/cn15/rd6 93 pmd0/cn58/re0 84 c3ina/sessend/pmd15/cn16/rd7 94 pmd1/cn59/re1 85 v cap 95 pma16/cn81/rg14 86 envreg 96 cn79/rg12 87 v busst /v cmpst 1/v busvld /pmd11/cn68/rf0 97 cn80/rg13 88 v cmpst 2/sessvld/pmd10/cn69/rf1 98 pmd2/cn60/re2 89 pmd9/cn78/rg1 99 pmd3/cn61/re3 90 pmd8/cn77/rg0 100 pmd4/cn62/re4 table 2: complete pin funct ion descriptions for 100- pin devices (continued) pinfunctionpinfunction legend: rpn and rpin represent remappable pins for peripheral pin select (pps) functions. note 1: alternate pin assignments for v ref + and v ref - when the altvref configuration bit is programmed. 2: alternate pin assignments for epmp when the altpmp configuration bit is programmed (only in 100-pin devices). 3: pin assignment for pmcsx when csf<1:0> is not equal to ? 00 ?.
pic24fj256gb210 family ds39975a-page 10 ? 2010 microchip technology inc. pin diagram ? top view (121-pin bga) (1) 13 5 10 11 a re4 re3 rg13 re0 rg0 rf1 envreg n/c rd12 rd2 rd1 b n/c rg15 re2 re1 ra7 rf0 v cap rd5 rd3 v ss rc14 c re6 v dd rg12 rg14 ra6 n/c rd7 rd4 v dd rc13 rd11 d rc1 re7 re5 v ss v ss n/c rd6 rd13 rd0 n/c rd10 e rc4 rc3 rg6 rc2 v dd rg1 n/c ra15 rd8 rd9 ra14 f mclr rg8 rg9 rg7 v ss n/c n/c v dd osci/ v ss osco/ g re8 re9 ra0 n/c v dd v ss v ss n/c ra5 ra3 ra4 h pgec3/ pged3/ v ss v dd n/c v dd n/c v bus /rf7 v usb d+/rg2 ra2 j rb3 rb2 pged2/rb7 av dd rb11 ra1 rb12 n/c n/c rf8 d-/rg3 k pgec1/ pged1/ ra10 rb8 n/c rf12 rb14 v dd rd15 usbid/ rf2 l pgec2/ ra9 av ss rb9 rb10rf13rb13 rb15 rd14 rf4 rf5 24 6 note 1: see table 3 for complete functional pinout descriptions. legend: rpn and rpin represent remappable pins for peripheral pin select functions. shaded pins indicate pins tolerant to up to +5.5v. rc12 rc15 rf3 rb5 rb4 rb1 rb0 rb6 9 8 7
? 2010 microchip technology inc. ds39975a-page 11 pic24fj256gb210 family table 3: complete pin function descriptions for 121-pin (bga) devices pinfunctionpinfunction a1 pmd4/cn62/re4 e5 v dd a2 pmd3/cn61/re3 e6 pmd9/cn78/rg1 a3 cn80/rg13 e7 n/c a4 pmd0/cn58/re0 e8 sda1/ rpi35 /pmbe1/cn44/ra15 a5 pmd8/cn77/rg0 e9 dmln/rtcc/ rp2 /cn53/rd8 a6 v cmpst 2/sessvld/pmd10/cn69/rf1 e10 dpln/ rp4 /pmack2/cn54/rd9 a7 envreg e11 scl1/ rpi36 /pma22/pmcs2 (2) /cn43/ra14 a8 n/c f1 mclr a9 rpi42 /pmd12/cn57/rd12 f2 an19/c2ind/ rp19 /pma3/pma21 (2) /cn10/rg8 a10 dph/ rp23 /pmack1/cn51/rd2 f3 an20/c2inc/ rp27 /pma2/cn11/rg9 a11 v cpcon / rp24 /v buschg /cn50/rd1 f4 an18/c1inc/ rp26 /pma4/pma20 (2) /cn9/rg7 b1 n/c f5 v ss b2 cn82/rg15 f6 n/c b3 pmd2/cn60/re2 f7 n/c b4 pmd1/cn59/re1 f8 v dd b5 an22/pma17/cn40/ra7 f9 osci/clki/cn23/rc12 b6 v busst /v cmpst 1/v busvld /pmd11/cn68/rf0 f10 v ss b7 v cap f11 osco/clko/cn22/rc15 b8 rp20 /pmrd/cn14/rd5 g1 rpi33 /pmcs1/cn66/re8 b9 rp22 /pmbe0/cn52/rd3 g2 an21/ rpi34 /pma19/cn67/re9 b10 v ss g3 tms/cn33/ra0 b11 sosco/sclki/t1ck/c3inc/ rpi37 /cn0/rc14 g4 n/c c1 scl3/pmd6/cn64/re6 g5 v dd c2 v dd g6 v ss c3 v sync /cn79/rg12 g7 v ss c4 pma16/cn81/rg14 g8 n/c c5 an23/cn39/ra6 g9 tdo/cn38/ra5 c6 n/c g10 sda2/pma20/pma4 (2) /cn36/ra3 c7 c3ina/sessend/pmd15/cn16/rd7 g11 tdi/pma21/pma3 (2) /cn37/ra4 c8 rp25 /pmwr/cn13/rd4 h1 pgec3/an5/c1ina/v buson / rp18 /cn7/rb5 c9 v dd h2 pged3/an4/c1inb/usboen/ rp28 /cn6/rb4 c10 sosci/c3ind/cn1/rc13 h3 v ss c11 rp12 /pma14/pmcs1 (3) /cn56/rd11 h4 v dd d1 rpi38 /cn45/rc1 h5 n/c d2 sda3/pmd7/cn65/re7 h6 v dd d3 pmd5/cn63/re5 h7 n/c d4 v ss h8 v bus /cn73/rf7 d5 v ss h9 v usb d6 n/c h10 d+/cn83/rg2 d7 c3inb/pmd14/cn15/rd6 h11 scl2/cn35/ra2 d8 pmd13/cn19/rd13 j1 an3/c2ina/vpio/cn5/rb3 d9 dmh/ rp11 /int0/cn49/rd0 j2 an2/c2inb/vmio/ rp13 /cn4/rb2 d10 n/c j3 pged2/an7/ rp7 /rcv/cn25/rb7 d11 rp3 /pma15/pmcs2 (3) /cn55/rd10 j4 av dd e1 an16/ rpi41 /pmcs2/pma22 (2) /cn48/rc4 j5 an11/pma12/cn29/rb11 e2 rpi40 /cn47/rc3 j6 tck/cn34/ra1 e3 an17/c1ind/ rp21 /pma5/pma18 (2) /cn8/rg6 j7 an12/pma11/ctedg2/cn30/rb12 e4 rpi39 /cn46/rc2 j8 n/c legend: rpn and rpin represent remappable pins for peripheral pin select functions. note 1: alternate pin assignments for v ref + and v ref - when the altvref configuration bit is programmed. 2: alternate pin assignments for epmp when the altpmp configuration bit is programmed (only in 100-pin devices). 3: pin assignment for pmcsx when csf<1:0> is not equal to ? 00 ?.
pic24fj256gb210 family ds39975a-page 12 ? 2010 microchip technology inc. j9 n/c l1 pgec2/an6/ rp6 /cn24/rb6 j10 rp15 /cn74/rf8 l2 v ref - (1) /pma7/cn41/ra9 j11 d-/cn84/rg3 l3 avss k1 pgec1/an1/v ref - (1) / rp1 /cn3/rb1 l4 an9/ rp9 /cn27/rb9 k2 pged1/an0/v ref + (1) / rp0 /cn2/rb0 l5 an10/cv ref /pma13/cn28/rb10 k3 v ref + (1) /pma6/cn42/ra10 l6 rp31 /cn76/rf13 k4 an8/ rp8 /cn26/rb8 l7 an13/pma10/ctedg1/cn31/rb13 k5 n/c l8 an15/refo/ rp29 /pma0/cn12/rb15 k6 rpi32 /pma18/pma5 (2) /cn75/rf12 l9 rpi43 /cn20/rd14 k7 an14/ctpls/ rp14 /pma1/cn32/rb14 l10 rp10 /pma9/cn17/rf4 k8 v dd l11 rp17 /pma8/scl2/cn18/rf5 k9 rp5 /cn21/rd15 ? ? k10 rp16 /usbid/cn71/rf3 ? ? k11 rp30 /cn70/rf2 ? ? table 3: complete pin function descriptions for 121-pin (bga) devices (continued) pinfunctionpinfunction legend: rpn and rpin represent remappable pins for peripheral pin select functions. note 1: alternate pin assignments for v ref + and v ref - when the altvref configuration bit is programmed. 2: alternate pin assignments for epmp when the altpmp configuration bit is programmed (only in 100-pin devices). 3: pin assignment for pmcsx when csf<1:0> is not equal to ? 00 ?.
? 2010 microchip technology inc. ds39975a-page 13 pic24fj256gb210 family table of contents 1.0 device overview ............................................................................................................. ........................................................... 15 2.0 guidelines for getting started with 16-bit microcontrollers................................................................. ....................................... 31 3.0 cpu ........................................................................................................................ ................................................................... 37 4.0 memory organization ......................................................................................................... ........................................................ 43 5.0 flash program memory........................................................................................................ ...................................................... 79 6.0 resets ...................................................................................................................... .................................................................. 85 7.0 interrupt controller ........................................................................................................ ............................................................. 91 8.0 oscillator configuration ....................................... ............................................................. ........................................................ 137 9.0 power-saving features....................................................................................................... ..................................................... 149 10.0 i/o ports .................................................................................................................. ................................................................. 151 11.0 timer1 ..................................................................................................................... ................................................................. 183 12.0 timer2/3 and timer4/5 ..................................................................................................... ....................................................... 185 13.0 input capture with dedicated timers ........................................................................................ ............................................... 191 14.0 output compare with dedicated timers ....................................................................................... ........................................... 195 15.0 serial peripheral interface (spi).......................................................................................... ..................................................... 205 16.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 217 17.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 225 18.0 universal serial bus with on-the-go support (usb otg) ...................................................................... ............................... 233 19.0 enhanced parallel master port (epmp) ....................................................................................... ............................................ 269 20.0 real-time clock and calendar (rtcc) ....................................................................................... ........................................... 281 21.0 32-bit programmable cyclic redundancy che ck (crc) generator ................................................................ ........................ 293 22.0 10-bit high-speed a/d converter ............................................................................................ ................................................ 301 23.0 triple comparator module................................................................................................... ..................................................... 311 24.0 comparator voltage reference............................................................................................... ................................................. 317 25.0 charge time measurement unit (ctmu) ........................................................................................ ........................................ 319 26.0 special features ........................................................................................................... ........................................................... 323 27.0 development support........................................................................................................ ....................................................... 335 28.0 instruction set summary .................................................................................................... ...................................................... 339 29.0 electrical characteristics ................................................................................................. ......................................................... 347 30.0 packaging information...................................................................................................... ........................................................ 363 appendix a: revision history................................................................................................... .......................................................... 375 index .......................................................................................................................... ....................................................................... 377 the microchip web site ......................................................................................................... ............................................................ 383 customer change notification service ........................................................................................... ................................................... 383 customer support............................................................................................................... ............................................................... 383 reader response ................................................................................................................ .............................................................. 384 product identification system .................................................................................................. .......................................................... 385
pic24fj256gb210 family ds39975a-page 14 ? 2010 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2010 microchip technology inc. ds39975a-page 15 pic24fj256gb210 family 1.0 device overview this document contains device-specific information for the following devices: the pic24fj256gb210 family enhances on the existing line of microchip?s 16-bit microcontrollers, adding a large data ram, up to 96 kbytes. the pic24fj256gb210 family allows the cpu to fetch data directly from an external memory device using the epmp module. 1.1 core features 1.1.1 16-bit architecture central to all pic24f devices is the 16-bit modified harvard architecture, first introduced with microchip?s dspic ? digital signal controllers (dscs). the pic24f cpu core offers a wide range of enhancements, such as: ? 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces ? linear addressing of up to 12 mbytes (program space) and 32 kbytes (data) ? a 16-element working register array with built-in software stack support ? a 17 x 17 hardware multiplier with support for integer math ? hardware support for 32 by 16-bit division ? an instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ?c? ? operational performance up to 16 mips 1.1.2 power-saving technology all of the devices in the pic24fj256gb210 family incorporate a range of features that can significantly reduce power consumption during operation. key items include: ? on-the-fly clock switching: the device clock can be changed under software control to the timer1 source or the internal, low-power rc oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. ? doze mode operation: when timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the cpu clock speed can be selectively reduced, allowing incremental power savings without missing a beat. ? instruction-based power-saving modes: the microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active with a single instruction in software. 1.1.3 oscillator options and features all of the devices in the pic24fj256gb210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. these include: ? two crystal modes using crystals or ceramic resonators. ? two external clock modes offering the option of a divide-by-2 clock output. ? a fast internal oscillator (frc) with a nominal 8 mhz output, which can also be divided under software control to provide clock speeds as low as 31 khz. ? a phase lock loop (pll) frequency multiplier, available to the external oscillator modes and the frc oscillator, which allows clock speeds of up to 32 mhz. ? a separate low-power internal rc oscillator (lprc) with a fixed 31 khz output, which provides a low-power option for timing-insensitive applications. the internal oscillator block also provides a stable reference source for the fail-safe clock monitor (fscm). this option constantly monitors the main clock source against a reference signal provided by the inter- nal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. the pic24f family is pin compatible with devices in the dspic33 family, and shares some compatibility with the pinout schema for pic18 and dspic30. this extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a microchip device. ? pic24fj128gb206 ? pic24fj256gb206 ? PIC24FJ128GB210 ? pic24fj256gb210
pic24fj256gb210 family ds39975a-page 16 ? 2010 microchip technology inc. 1.2 usb on-the-go the usb on-the-go (usb otg) module provides on-chip functionality as a target device, compatible with the usb 2.0 standard, as well as limited stand-alone functionality as a usb embedded host. by implement- ing usb host negotiation protocol (hnp), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile usb enabled applications on a microcontroller platform. in addition to usb host functionality, pic24fj256gb210 family devices provide a true single chip usb solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. 1.3 other special features ? peripheral pin select: the peripheral pin select (pps) feature allows most digital peripherals to be mapped over a fixed set of digital i/o pins. users may independently map the input and/or output of any one of the many digital peripherals to any one of the i/o pins. ? communications: the pic24fj256gb210 family incorporates a range of serial communication peripherals to handle a range of application requirements. there are three independent i 2 c? modules that support both master and slave modes of operation. devices also have, through the pps feature, four independent uarts with built-in irda ? encoders/decoders and three spi modules. ? analog features: all members of the pic24fj256gb210 family include a 10-bit a/d converter (adc) module and a triple comparator module. the adc module incorporates program- mable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speeds. the comparator module includes three analog comparators that are configurable for a wide range of operations. ? ctmu interface: in addition to their other analog features, members of the pic24fj256gb210 family include the ctmu interface module. this provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. ? enhanced parallel master/parallel slave port: there are general purpose i/o ports, which can be configured for parallel data communications. in this mode, the device can be master or slave on the communication bus. 4-bit, 8-bit and 16-bit data transfers, with up to 23 external address lines, are supported in master modes. ? real-time clock and calendar: (rtcc) this module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.4 details on individual family members devices in the pic24fj256gb210 family are available in 64-pin and 100-pin packages. the general block diagram for all devices is shown in figure 1-1. the devices are differentiated from each other in seven ways: 1. flash program memory (128 kbytes for pic24fj128gb2xx devices and 256 kbytes for pic24fj256gb2xx devices). 2. available i/o pins and ports (52 pins on 6 ports for pic24fjxxxgb2xx devices and 84 pins on 7 ports for pic24fjxxxgb2xx devices). 3. available interrupt-on-change notification (icn) inputs (52 on pic24fjxxxgb2xx devices and 84 on pic24fjxxxgb2xx devices). 4. available remappable pins (29 pins on pic24fjxxxgb2xx devices and 44 pins on pic24fjxxxgb2xx devices). 5. analog channels for adc (16 channels for pic24fjxxxgb206 devices and 24 channels for pic24fjxxxgb2xx devices). all other features for devices in this family are identical. these are summarized in table 1-1 and table 1-2. a list of the pin features available on the pic24fj256gb210 family devices, sorted by function, is shown in table 1-1. note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. this information is provided in the pinout diagrams in the beginning of the data sheet. multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
? 2010 microchip technology inc. ds39975a-page 17 pic24fj256gb210 family table 1-1: device features for th e pic24fj256gb210 family: 64-pin features pic24fj128gb206 pic24fj256gb206 operating frequency dc ? 32 mhz program memory (bytes) 128k 256k program memory (instructions) 44,032 87,552 data memory (bytes) 96k interrupt sources (soft vectors/nmi traps) 65 (61/4) i/o ports ports b, c, d, e, f, g total i/o pins 52 remappable pins 29 (28 i/o, 1 input only) timers: total number (16-bit) 5 (1) 32-bit (from paired 16-bit timers) 2 input capture channels 9 (1) output compare/pwm channels 9 (1) input change notification interrupt 52 serial communications: uart 4 (1) spi (3-wire/4-wire) 3 (1) i 2 c? 3 parallel communications (epmp/psp) yes jtag boundary scan yes 10-bit analog-to-digital converter (adc) module (input channels) 16 analog comparators 3 ctmu interface yes usb otg yes resets (and delays) por, bor, reset instruction, mclr , wdt; illegal opcode, repeat instruction, hardware traps, configuration word mismatch (ost, pll lock) instruction set 76 base instructions, multiple addressing mode variations packages 64-pin tqfp and qfn note 1: peripherals are accessible through remappable pins.
pic24fj256gb210 family ds39975a-page 18 ? 2010 microchip technology inc. table 1-2: device features for the pi c24fj256gb210 family: 100-pin devices features PIC24FJ128GB210 pic24fj256gb210 operating frequency dc ? 32 mhz program memory (bytes) 128k 256k program memory (instructions) 44,032 87,552 data memory (bytes) 96k interrupt sources (soft vectors/nmi traps) 65 (61/4) i/o ports ports a, b, c, d, e, f, g total i/o pins 84 remappable pins 44 (32 i/o, 12 input only) timers: total number (16-bit) 5 (1) 32-bit (from paired 16-bit timers) 2 input capture channels 9 (1) output compare/pwm channels 9 (1) input change notification interrupt 84 serial communications: uart 4 (1) spi (3-wire/4-wire) 3 (1) i 2 c? 3 parallel communications (epmp/psp) yes jtag boundary scan yes 10-bit analog-to-digital converter (adc) module (input channels) 24 analog comparators 3 ctmu interface yes usb otg yes resets (and delays) por, bor, reset instruction, mclr , wdt; illegal opcode, repeat instruction, hardware traps, configuration word mismatch (ost, pll lock) instruction set 76 base instructions, multiple addressing mode variations packages 100-pin tqfp and 121-pin bga note 1: peripherals are accessible through remappable pins.
? 2010 microchip technology inc. ds39975a-page 19 pic24fj256gb210 family figure 1-1: pic24fj256gb210 fa mily general block diagram instruction decode and control 16 pch pcl 16 program counter 16-bit alu 23 24 data bus inst register 16 divide support inst latch 16 ea mux read agu write agu 16 16 8 interrupt controller eds and table data access control block stack control logic repeat control logic data latch data ram address latch address latch extended data data latch 16 address bus literal data 23 control signals 16 16 16 x 16 w reg array multiplier 17x17 osci/clki osco/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer lvd & bor precision reference band gap frc/lprc oscillators regulator voltage v cap envreg porta (1) portc (1) (12 i/o) (8 i/o) portb (16 i/o) note 1: not all i/o pins or features are implemented on all device pinout configurations. see table 1-1 for specific implementations by pin count . 2: these peripheral i/os are only accessible through remappable pins. portd (1) (16 i/o) comparators (2) timer2/3 (2) timer1 rtcc ic adc 10-bit oc/pwm spi i 2 c timer4/5 (2) ? epmp/psp 1-9 (2) icns (1) uart refo porte (1) portg (1) (10 i/o) (12 i/o) portf (1) (10 i/o) 1/2/3 (2) 1/2/3 1/2/3/4 (2) 1-9 (2) ctmu (2) usb otg up to 0x7fff space program memory/
pic24fj256gb210 family ds39975a-page 20 ? 2010 microchip technology inc. table 1-3: pic24fj256gb210 fa mily pinout descriptions function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga an0 16 25 k2 i ana a/d analog inputs. an1 15 24 k1 i ana an2 14 23 j2 i ana an3 13 22 j1 i ana an4 12 21 h2 i ana an5 11 20 h1 i ana an6 17 26 l1 i ana an7 18 27 j3 i ana an8 21 32 k4 i ana an9 22 33 l4 i ana an10 23 34 l5 i ana an11 24 35 j5 i ana an12 27 41 j7 i ana an13 28 42 l7 i ana an14 29 43 k7 i ana an15 30 44 l8 i ana an16 ? 9 e1 i ana an17 ? 10 e3 i ana an18 ? 11 f4 i ana an19 ? 12 f2 i ana an20 ? 14 f3 i ana an21 ? 19 g2 i ana an22 ? 92 b5 i ana an23 ? 91 c5 i ana av dd 19 30 j4 p ? positive supply for analog modules. av ss 20 31 l3 p ? ground reference for analog modules. c1ina 11 20 h1 i ana comparator 1 input a. c1inb 12 21 h2 i ana comparator 1 input b. c1inc 5 11 f4 i ana comparator 1 input c. c1ind 4 10 e3 i ana comparator 1 input d. c2ina 13 22 j1 i ana comparator 2 input a. c2inb 14 23 j2 i ana comparator 2 input b. c2inc 8 14 f3 i ana comparator 2 input c. c2ind 6 12 f2 i ana comparator 2 input d. c3ina 55 84 c7 i ana comparator 3 input a. c3inb 54 83 d7 i ana comparator 3 input b. c3inc 48 74 b11 i ana comparator 3 input c. c3ind 47 73 c10 i ana comparator 3 input d. clki 39 63 f9 i st main clock input connection. clko 40 64 f11 o ? system clock output. legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 21 pic24fj256gb210 family cn0 48 74 b11 i st interrupt-on-change inputs. cn1 47 73 c10 i st cn2 16 25 k2 i st cn3 15 24 k1 i st cn4 14 23 j2 i st cn5 13 22 j1 i st cn6 12 21 h2 i st cn7 11 20 h1 i st cn8 4 10 e3 i st cn9 5 11 f4 i st cn10 6 12 f2 i st cn11 8 14 f3 i st cn12 30 44 l8 i st cn13 52 81 c8 i st cn14 53 82 b8 i st cn15 54 83 d7 i st cn16 55 84 c7 i st cn17 31 49 l10 i st cn18 32 50 l11 i st cn19 ? 80 d8 i st cn20 ? 47 l9 i st cn21 ? 48 k9 i st cn22 40 64 f11 i st cn23 39 63 f9 i st cn24 17 26 l1 i st cn25 18 27 j3 i st cn26 21 32 k4 i st cn27 22 33 l4 i st cn28 23 34 l5 i st cn29 24 35 j5 i st cn30 27 41 j7 i st cn31 28 42 l7 i st cn32 29 43 k7 i st cn33 ? 17 g3 i st cn34 ? 38 j6 i st cn35 ? 58 h11 i st cn36 ? 59 g10 i st cn37 ? 60 g11 i st cn38 ? 61 g9 i st cn39 ? 91 c5 i st table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
pic24fj256gb210 family ds39975a-page 22 ? 2010 microchip technology inc. cn40 ? 92 b5 i st interrupt-on-change inputs. cn41 ? 28 l2 i st cn42 ? 29 k3 i st cn43 ? 66 e11 i st cn44 ? 67 e8 i st cn45 ? 6 d1 i st cn46 ? 7 e4 i st cn47 ? 8 e2 i st cn48 ? 9 e1 i st cn49 46 72 d9 i st cn50 49 76 a11 i st cn51 50 77 a10 i st cn52 51 78 b9 i st cn53 42 68 e9 i st cn54 43 69 e10 i st cn55 44 70 d11 i st cn56 45 71 c11 i st cn57 ? 79 a9 i st cn58 60 93 a4 i st cn59 61 94 b4 i st cn60 62 98 b3 i st cn61 63 99 a2 i st cn62 64 100 a1 i st cn63 1 3 d3 i st cn64 2 4 c1 i st cn65 3 5 d2 i st cn66 ? 18 g1 i st cn67 ? 19 g2 i st cn68 58 87 b6 i st cn69 59 88 a6 i st cn70 ? 52 k11 i st cn71 33 51 k10 i st cn73 ? 54 h8 i st cn74 ? 53 j10 i st cn75 ? 40 k6 i st cn76 ? 39 l6 i st cn77 ? 90 a5 i st cn78 ? 89 e6 i st cn79 ? 96 c3 i st cn80 ? 97 a3 i st table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 23 pic24fj256gb210 family cn81 ? 95 c4 i st interrupt-on-change inputs. cn82 ? 1 b2 i st cn83 37 57 h10 i st cn84 36 56 j11 i st ctedg1 28 42 l7 i ana ctmu external edge input 1. ctedg2 27 41 j7 i ana ctmu external edge input 2. ctpls 29 43 k7 o ? ctmu pulse output. cv ref 23 34 l5 o ? comparator voltage reference output. d+ 37 57 h10 i/o ? usb differential plus line (internal transceiver). d- 36 56 j11 i/o ? usb differential minus line (internal transceiver). dmh 46 72 d9 o ? d- external pull-up control output. dmln 42 68 e9 o ? d- external pull-down control output. dph 50 77 a10 o ? d+ external pull-up control output. dpln 43 69 e10 o ? d+ external pull-down control output. envreg 57 86 j7 i st voltage regulator enable. int0 46 72 d9 i st external interrupt input. mclr 7 13 f1 i st master clear (device reset) input. this line is brought low to cause a reset. osci 39 63 f9 i ana main oscillator input connection. osco 40 64 f11 o ana main oscillator output connection. pgec1 15 24 k1 i/o st in-circuit debugger/emulator/icsp? programming clock 1. pged1 16 25 k2 i/o st in-circuit debugger/emulator/icsp programming data 1. pgec2 17 26 l1 i/o st in-circuit debugger/emulator/icsp programming clock 2. pged2 18 27 j3 i/o st in-circuit debugger/emulator/icsp programming data 2. pgec3 11 20 h1 i/o st in-circuit debugger/emulator/icsp programming clock 3. pged3 12 21 h2 i/o st in-circuit debugger/emulator/icsp programming data 3. table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
pic24fj256gb210 family ds39975a-page 24 ? 2010 microchip technology inc. pma0 30 44 l8 i/o st parallel master port address bit 0 input (buffered slave modes) and output (master modes). pma1 29 43 k7 i/o st parallel master port address bit 1 input (buffered slave modes) and output (master modes). pma2 8 14 f3 o ? parallel master port address bits<22:2>. pma3 6 12, 60 (1) f2, g11 (1) o? pma4 5 11,59 (1) f4,g10 (1) o? pma5 4 10,40 (1) e3,k6 (1) o? pma6 16 29 k3 o ? pma7 22 28 l2 o ? pma8 32 50 l11 o ? pma9 31 49 l10 o ? pma10 28 42 l7 o ? pma11 27 41 j7 o ? pma12 24 35 j5 o ? pma13 23 34 l5 o ? pma14 45 71 c11 o ? pma15 44 70 d11 o ? pma16 ? 95 c4 o ? pma17 ? 92 b5 o ? pma18 ? 40,10 (1) k6,e3 (1) o? pma19 ? 19 g2 o ? pma20 ? 59, 11 (1) g10, f4 (1) o? pma21 ? 60,12 (1) g11,f2 (1) o? pma22 ? 66,9 (1) e11,e1 (1) o? pmack1 50 77 a10 i st/ttl parallel master port acknowledge input 1. pmack2 43 69 e10 i st/ttl parallel master port acknowledge input 2. pmall 30 44 l8 o ? parallel master port lower address latch strobe. pmalh 29 43 k7 o ? parallel master port higher address latch strobe. pmalu ? 14 f3 o ? parallel master port upper address latch strobe. pmbe0 51 78 b9 o ? parallel master port byte enable strobe 0. pmbe1 ? 67 e8 o ? parallel master port byte enable strobe 1. pmcs1 45 71 (3) ,18 c11 (3) ,g1 i/o st/ttl parallel master port chip select strobe 1. pmcs2 44 70 (2) ,9, 66 (1) d11 (2) ,e1, e11 (1) o ? parallel master port chip select strobe 2. table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 25 pic24fj256gb210 family pmd0 60 93 a4 i/o st/ttl parallel master port data bits<15:0>. pmd1 61 94 b4 i/o st/ttl pmd2 62 98 b3 i/o st/ttl pmd3 63 99 a2 i/o st/ttl pmd4 64 100 a1 i/o st/ttl pmd5 1 3 d3 i/o st/ttl pmd6 2 4 c1 i/o st/ttl pmd7 3 5 d2 i/o st/ttl pmd8 ? 90 a5 i/o st/ttl pmd9 ? 89 e6 i/o st/ttl pmd10 ? 88 a6 i/o st/ttl pmd11 ? 87 b6 i/o st/ttl pmd12 ? 79 a9 i/o st/ttl pmd13 ? 80 d8 i/o st/ttl pmd14 ? 83 d7 i/o st/ttl pmd15 ? 84 c7 i/o st/ttl pmrd 53 82 b8 i/o st/ttl parallel master port read strobe. pmwr 52 81 c8 i/o st/ttl parallel master port write strobe. ra0 ? 17 g3 i/o st porta digital i/o. ra1 ? 38 j6 i/o st ra2 ? 58 h11 i/o st ra3 ? 59 g10 i/o st ra4 ? 60 g11 i/o st ra5 ? 61 g9 i/o st ra6 ? 91 c5 i/o st ra7 ? 92 b5 i/o st ra9 ? 28 l2 i/o st ra10 ? 29 k3 i/o st ra14 ? 66 e11 i/o st ra15 ? 67 e8 i/o st table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
pic24fj256gb210 family ds39975a-page 26 ? 2010 microchip technology inc. rb0 16 25 k2 i/o st portb digital i/o. rb1 15 24 k1 i/o st rb2 14 23 j2 i/o st rb3 13 22 j1 i/o st rb4 12 21 h2 i/o st rb5 11 20 h1 i/o st rb6 17 26 l1 i/o st rb7 18 27 j3 i/o st rb8 21 32 k4 i/o st rb9 22 33 l4 i/o st rb10 23 34 l5 i/o st rb11 24 35 j5 i/o st rb12 27 41 j7 i/o st rb13 28 42 l7 i/o st rb14 29 43 k7 i/o st rb15 30 44 l8 i/o st rc1 ? 6 d1 i/o st portc digital i/o. rc2 ? 7 e4 i/o st rc3 ? 8 e2 i/o st rc4 ? 9 e1 i/o st rc12 39 63 f9 i/o st rc13 47 73 c10 i/o st rc14 48 74 b11 i/o st rc15 40 64 f11 i/o st rcv 18 27 j3 i st usb receive input (from external transceiver). table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 27 pic24fj256gb210 family rd0 46 72 d9 i/o st portd digital i/o. rd1 49 76 a11 i/o st rd2 50 77 a10 i/o st rd3 51 78 b9 i/o st rd4 52 81 c8 i/o st rd5 53 82 b8 i/o st rd6 54 83 d7 i/o st rd7 55 84 c7 i/o st rd8 42 68 e9 i/o st rd9 43 69 e10 i/o st rd10 44 70 d11 i/o st rd11 45 71 c11 i/o st rd12 ? 79 a9 i/o st rd13 ? 80 d8 i/o st rd14 ? 47 l9 i/o st rd15 ? 48 k9 i/o st re0 60 93 a4 i/o st porte digital i/o. re1 61 94 b4 i/o st re2 62 98 b3 i/o st re3 63 99 a2 i/o st re4 64 100 a1 i/o st re5 1 3 d3 i/o st re6 2 4 c1 i/o st re7 3 5 d2 i/o st re8 ? 18 g1 i/o st re9 ? 19 g2 i/o st refo 30 44 l8 o ? reference clock output. rf0 58 87 b6 i/o st portf digital i/o. rf1 59 88 a6 i/o st rf2 ? 52 k11 i/o st rf3 33 51 k10 i/o st rf4 31 49 l10 i/o st rf5 32 50 l11 i/o st rf7 34 54 h8 i/o st rf8 ? 53 j10 i/o st rf12 ? 40 k6 i/o st rf13 ? 39 l6 i/o st table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
pic24fj256gb210 family ds39975a-page 28 ? 2010 microchip technology inc. rg0 ? 90 a5 i/o st portg digital i/o. rg1 ? 89 e6 i/o st rg2 37 57 h10 i/o st rg3 36 56 j11 i/o st rg6 4 10 e3 i/o st rg7 5 11 f4 i/o st rg8 6 12 f2 i/o st rg9 8 14 f3 i/o st rg12 ? 96 c3 i/o st rg13 ? 97 a3 i/o st rg14 ? 95 c4 i/o st rg15 ? 1 b2 i/o st rp0 16 25 k2 i/o st remappable peripheral (input or output). rp1 15 24 k1 i/o st rp2 42 68 e9 i/o st rp3 44 70 d11 i/o st rp4 43 69 e10 i/o st rp5 ? 48 k9 i/o st rp6 17 26 l1 i/o st rp7 18 27 j3 i/o st rp8 21 32 k4 i/o st rp9 22 33 l4 i/o st rp10 31 49 l10 i/o st rp11 46 72 d9 i/o st rp12 45 71 c11 i/o st rp13 14 23 j2 i/o st rp14 29 43 k7 i/o st rp15 ? 53 j10 i/o st rp16 33 51 k10 i/o st rp17 32 50 l11 i/o st rp18 11 20 h1 i/o st rp19 6 12 f2 i/o st table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 29 pic24fj256gb210 family rp20 53 82 b8 i/o st remappable peripheral (input or output). rp21 4 10 e3 i/o st rp22 51 78 b9 i/o st rp23 50 77 a10 i/o st rp24 49 76 a11 i/o st rp25 52 81 c8 i/o st rp26 5 11 f4 i/o st rp27 8 14 f3 i/o st rp28 12 21 h2 i/o st rp29 30 44 l8 i/o st rp30 ? 52 k11 i/o st rp31 ? 39 l6 i/o st rpi32 ? 40 k6 i st remappable peripheral (input only). rpi33 ? 18 g1 i st rpi34 ? 19 g2 i st rpi35 ? 67 e8 i st rpi36 ? 66 e11 i st rpi37 48 74 b11 i st rpi38 ? 6 d1 i st rpi39 ? 7 e4 i st rpi40 ? 8 e2 i st rpi41 ? 9 e1 i st rpi42 ? 79 a9 i st rpi43 ? 47 l9 i st rtcc 42 68 e9 o ? real-time clock alarm/seconds pulse output. scl1 44 66 e11 i/o i 2 c? i2c1 synchronous serial clock input/output. scl2 32 58 h11 i/o i 2 c i2c2 synchronous serial clock input/output. scl3 2 4 c1 i/o i 2 c i2c3 synchronous serial clock input/output. sclki 48 74 b11 o ana secondary clock input. sda1 43 67 e8 i/o i 2 c i2c1 data input/output. sda2 31 59 g10 i/o i 2 c i2c2 data input/output. sda3 3 5 d2 i/o i 2 c i2c3 data input/output. sessend 55 84 c7 i st usb v bus boost generator, comparator input 3. sessvld 59 88 a6 i st usb v bus boost generator, comparator input 2. sosci 47 73 c10 i ana secondary oscillator/timer1 clock input. sosco 48 74 b11 o ana secondary oscillator/timer1 clock output. t1ck 48 74 b11 i st timer1 clock. table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
pic24fj256gb210 family ds39975a-page 30 ? 2010 microchip technology inc. tck 27 38 j6 i st jtag test clock input. tdi 28 60 g11 i st jtag test data input. tdo 24 61 g9 o ? jtag test data output. tms 23 17 g3 i st jtag test mode select input. usbid 33 51 k10 i st usb otg id (otg mode only). usboen 12 21 h2 o ? usb output enable control (for external transceiver). v bus 34 54 h8 i ana usb voltage, host mode (5v). v buschg 49 76 a11 o ? external usb v bus charge output. v buson 11 20 h1 o ? usb otg external charge pump control. v busst 58 87 b6 i ana usb otg internal charge pump feedback control. v busvld 58 87 b6 i st usb v bus boost generator, comparator input 1. v cap 56 85 b7 p ? external filter capacitor connection (regulator enabled). v cmpst 1 58 87 b6 i st usb v bus boost generator, comparator input 1. v cmpst 2 59 88 a6 i st usb v bus boost generator, comparator input 2. v cpcon 49 76 a11 o ? usb otg v bus pwm/charge output. v dd 10, 26, 38 2, 16, 37, 46, 62 c2, c9, f8, g5, h6, k8, h4, e5 p ? positive supply for peripheral digital logic and i/o pins. vmio 14 23 j2 i st usb differential minus input/output (external transceiver). vpio 13 22 j1 i st usb differential plus input/output (external transceiver). v ref -1528, 24 (4) l2, k1 (4) i ana a/d and comparator reference voltage (low) input. v ref +1629, 25 (4) k3, k2 (4) i ana a/d and comparator reference voltage (high) input. v ss 9, 25, 41 15, 36, 45, 65, 75 b10, f5, f10, g6, g7, h3, d4, d5 p ? ground reference for logic and i/o pins. v usb 35 55 h9 p ? usb voltage (3.3v). table 1-3: pic24fj256gb210 family pinout descriptions (continued) function pin number i/o input buffer description 64-pin tqfp/qfn 100-pin tqfp 121-pin bga legend: ttl = ttl input buffer st = schmitt trigger input buffer ana = analog level input/output i 2 c? = i 2 c/smbus input buffer note 1: the alternate epmp pins are selected when the altpmp (cw3<12>) bit is programmed to ? 0 ?. 2: the pmsc2 signal will replace the pma15 signal on the 15-pin pma when csf<1:0> = 01 or 10 . 3: the pmcs1 signal will replace the pma14 signal on the 14-pin pma when csf<1:0> = 10 . 4: the alternate v ref pins selected when the altvref (cw1<5>) bit is programmed to ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 31 pic24fj256gb210 family 2.0 guidelines for getting started with 16-bit microcontrollers 2.1 basic connection requirements getting started with the pic24fj256gb210 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. the following pins must always be connected: ?all v dd and v ss pins (see section 2.2 ?power supply pins? ) ?all av dd and av ss pins, regardless of whether or not the analog device features are used (see section 2.2 ?power supply pins? ) ?mclr pin (see section 2.3 ?master clear (mclr) pin? ) ? envreg and v cap pins (pic24fj devices only) (see section 2.4 ?voltage regulator pins (envreg and v cap )? ) these pins must also be connected if they are being used in the end application: ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osci and osco pins when an external oscillator source is used (see section 2.6 ?external oscillator pins? ) additionally, the following pins may be required: ?v ref +/v ref - pins used when external voltage reference for analog modules is implemented the minimum mandatory connections are shown in figure 2-1. figure 2-1: recommended minimum connections note: the av dd and av ss pins must always be connected, regardless of whether any of the analog modules are being used. pic24fxxxx v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c1 r1 v dd mclr v cap r2 envreg (1) c7 c2 (2) c3 (2) c4 (2) c5 (2) c6 (2) key (all values are recommendations): c1 through c6: 0.1 ? f, 20v ceramic c7: 10 ? f, 6.3v or greater, tantalum or ceramic r1: 10 k ? r2: 100 ? to 470 ? note 1: see section 2.4 ?voltage regulator pins (envreg and v cap )? for explanation of envreg pin connections. 2: the example shown is for a pic24f device with five v dd /v ss and av dd /av ss pairs. other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. (1)
pic24fj256gb210 family ds39975a-page 32 ? 2010 microchip technology inc. 2.2 power supply pins 2.2.1 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a 0.1 ? f (100 nf), 10-20v capacitor is recommended. the capacitor should be a low-esr device with a resonance frequency in the range of 200 mhz and higher. ceramic capacitors are recommended. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). ? handling high-frequency noise: if the board is experiencing high-frequency noise (upward of tens of mhz), add a second ceramic type capaci- tor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 ? f to 0.001 ? f. place this second capacitor next to each primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 ? f in parallel with 0.001 ? f). ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb trace inductance. 2.2.2 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 ? f to 47 ? f. 2.3 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset, and device programming and debugging. if programming and debugging are not required in the end application, a direct connection to v dd may be all that is required. the addition of other components, to help increase the application?s resistance to spurious resets from voltage sags, may be beneficial. a typical configuration is shown in figure 2-1. other circuit designs may be implemented, depending on the application?s requirements. during programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r1 and c1 will need to be adjusted based on the application and pcb requirements. for example, it is recommended that the capacitor, c1, be isolated from the mclr pin during programming and debugging operations by using a jumper (figure 2-2). the jumper is replaced for normal run-time operations. any components associated with the mclr pin should be placed within 0.25 inch (6 mm) of the pin. figure 2-2: example of mclr pin connections note 1: r1 ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r2 ? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c1 r2 r1 v dd mclr pic24fxxxx jp
? 2010 microchip technology inc. ds39975a-page 33 pic24fj256gb210 family 2.4 voltage regulator pins (envreg and v cap ) the on-chip voltage regulator enable pin (envreg) must always be connected directly to a supply voltage. refer to section 26.2 ?on-chip voltage regulator? for details on connecting and using the on-chip regulator. when the regulator is enabled, a low-esr (<5 ? ) capacitor is required on the v cap pin to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must use a capacitor of 10 ? f connected to ground. the type can be ceramic or tantalum. a suitable example is the murata grm21bf50j106ze01 (10 ? f, 6.3v) or equivalent. designers may use figure 2-3 to evaluate esr equivalence of candidate devices. the placement of this capacitor should be close to v cap . it is recommended that the trace length not exceed 0.25 inch (6 mm). refer to section 29.0 ?electrical characteristics? for additional information. figure 2-3: frequency vs. esr performance for suggested v cap 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ? . pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. for device emulation, ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical connections for the icsp to the microchip debugger/emulator tool. for more information on available microchip development tools connection requirements, refer to section 27.0 ?development support? . note: this section applies only to pic24fj devices with an on-chip voltage regulator. 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 frequency (mhz) esr ( ? ) note: data for murata grm21bf50j106ze01 shown. measurements at 25c, 0v dc bias.
pic24fj256gb210 family ds39975a-page 34 ? 2010 microchip technology inc. 2.6 external oscillator pins many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 ?oscillator configuration? for details). the oscillator circuit should be placed on the same side of the board as the device. place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. layout suggestions are shown in figure 2-4. in-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. with fine-pitch packages, it is not always possible to com- pletely surround the pins and components. a suitable solution is to tie the broken guard sections to a mirrored ground layer. in all cases, the guard trace(s) must be returned to ground. in planning the application?s routing and i/o assign- ments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times and other similar noise). for additional information and design guidance on oscillator circuits, please refer to these microchip application notes, available at the corporate web site (www.microchip.com): ? an826, ?crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices? ? an849, ?basic picmicro ? oscillator design? ? an943, ?practical picmicro ? oscillator analysis and design? ? an949, ?making your oscillator work? figure 2-4: suggested placement of the oscillator circuit gnd ` ` ` osci osco sosco sosc i copper pour primary oscillator crystal secondary crystal device pins primary oscillator c1 c2 sec oscillator: c1 sec oscillator: c2 (tied to ground) gnd osco osci bottom layer copper pour oscillator crystal top layer copper pour c2 c1 device pins (tied to ground) (tied to ground) single-sided and in-line layouts: fine-pitch (dual-sided) layouts: oscillator
? 2010 microchip technology inc. ds39975a-page 35 pic24fj256gb210 family 2.7 configuration of analog and digital pins during icsp operations if an icsp compliant emulator is selected as a debug- ger, it automatically initializes all of the a/d input pins (anx) as ?digital? pins. depending on the particular device, this is done by clearing all bit in the ansx reg- isters. all pic24fj devices will have several ansx registers (one for each port). refer to ( section 10.0 ?i/o ports? ) for more specific information. the bits in these registers that correspond to the a/d pins that initialized the emulator must not be changed by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain a/d pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the adc module, as follows: ? set the bits corresponding to the pin(s) to be con- figured as analog. do not change any other bits, particularly those corresponding to the pgecx/pgedx pair, at any time. when a microchip debugger/emulator is used as a programmer, the user application firmware must correctly configure the ansx registers. automatic initialization of this register is only done during debugger operation. failure to correctly configure the register(s) will result in all a/d pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.8 unused i/os unused i/o pins should be configured as outputs and driven to a logic low state. alternatively, connect a 1 k ? to 10 k ? resistor to v ss on unused pins and drive the output to logic low.
pic24fj256gb210 family ds39975a-page 36 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 37 pic24fj256gb210 family 3.0 cpu the pic24f cpu has a 16-bit (data) modified harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m instructions of user program memory space. a single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the repeat instructions, which are interruptible at any point. pic24f devices have sixteen, 16-bit working registers in the programmer?s model. each of the working registers can act as a data, address or address offset register. the 16 th working register (w15) operates as a software stack pointer for interrupts and calls. the lower 32 kbytes of the data space can be accessed linearly. the upper 32 kbytes of the data space are referred to as extended data space to which the extended data ram, epmp memory space or program memory can be mapped. the instruction set architecture (isa) has been significantly enhanced beyond that of the pic18, but maintains an acceptable level of backward compatibil- ity. all pic18 instructions and addressing modes are supported, either directly, or through simple macros. many of the isa enhancements have been driven by compiler efficiency needs. the core supports inherent (no operand), relative, literal, memory direct addressing modes along with three groups of addressing modes. all modes support register direct and various register indirect modes. each group offers up to seven addressing modes. instructions are associated with predefined addressing modes depending upon their functional requirements. for most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing trinary operations (that is, a + b = c) to be executed in a single cycle. a high-speed, 17-bit x 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. the multiplier supports signed, unsigned and mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer multiplication. all multiply instructions execute in a single cycle. the 16-bit alu has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. it operates in conjunction with the repeat instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. all divide operations require 19 cycles to complete but are interruptible at any cycle boundary. the pic24f has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 inter- rupt sources. each interrupt source can be assigned to one of seven priority levels. a block diagram of the cpu is shown in figure 3-1. 3.1 programmer?s model the programmer?s model for the pic24f is shown in figure 3-2. all registers in the programmer?s model are memory mapped and can be manipulated directly by instructions. a description of each register is provided in table 3-1. all registers associated with the programmer?s model are memory mapped. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 44. ?cpu with extended data space (eds)? (ds39732). the informa- tion in this data sheet supersedes the information in the frm.
pic24fj256gb210 family ds39975a-page 38 ? 2010 microchip technology inc. figure 3-1: pic24f cp u core block diagram table 3-1: cpu core registers register(s) name description w0 through w15 working register array pc 23-bit program counter sr alu status register splim stack pointer limit value register tblpag table memory page address register rcount repeat loop counter register corcon cpu control register disicnt disable interrupt count register dsrpag data space read page register dswpag data space write page register instruction decode and control pch pcl 16 program counter 16-bit alu 23 23 24 23 data bus instruction reg 16 16 x 16 w register array divide support rom latch 16 ea mux ragu wagu 16 16 8 interrupt controller eds and table data access control block stack control logic loop control logic data latch data ram address latch control signals to various blocks program memory/ data latch address bus 16 literal data 16 16 hardware multiplier 16 to peripheral modules address latch up to 0x7fff extended data space
? 2010 microchip technology inc. ds39975a-page 39 pic24fj256gb210 family figure 3-2: programmer?s model n ov z c tblpag 22 0 7 0 0 15 program counter table memory page alu status register (sr) working/address registers w0 (wreg) w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 frame pointer stack pointer ra 0 rcount 15 0 repeat loop counter splim stack pointer limit srl 0 0 15 0 cpu control register (corcon) srh w14 w15 dc ipl 210 ?? ? ? ? ? ? pc divider working registers multiplier registers 15 0 value register address register register data space read page register data space write page register disable interrupt count register 13 0 disicnt 90 dsrpag 80 dswpag ipl3 ???????????? registers or bits are shadowed for push.s and pop.s instructions. ???
pic24fj256gb210 family ds39975a-page 40 ? 2010 microchip technology inc. 3.2 cpu control registers register 3-1: sr: alu status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hsc ? ? ? ? ? ? ?dc bit 15 bit 8 r/w-0, hsc (1) r/w-0, hsc (1) r/w-0, hsc (1) r-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc ipl2 (2) ipl1 (2) ipl0 (2) ra n ov z c bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 dc: alu half carry/borrow bit 1 = a carry out from the 4 th low-order bit (for byte-sized data) or 8 th low-order bit (for word-sized data) of the result occurred 0 = no carry out from the 4 th or 8 th low-order bit of the result has occurred bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (1,2) 111 = cpu interrupt priority level is 7 (15); user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: alu negative bit 1 = result was negative 0 = result was not negative (zero or positive) bit 2 ov: alu overflow bit 1 = overflow occurred for signed (2?s complement) arithmetic in this arithmetic operation 0 = no overflow has occurred bit 1 z: alu zero bit 1 = an operation, which affects the z bit, has set it at some time in the past 0 = the most recent operation, which affects the z bit, has cleared it (i.e., a non-zero result) bit 0 c: alu carry/borrow bit 1 = a carry out from the most significant bit of the result occurred 0 = no carry out from the most significant bit of the result occurred note 1: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . 2: the ipl status bits are concatenated with the ipl3 (corcon<3>) bit to form the cpu interrupt priority level (ipl). the value in parentheses indicates the ipl when ipl3 = 1 .
? 2010 microchip technology inc. ds39975a-page 41 pic24fj256gb210 family 3.3 arithmetic logic unit (alu) the pic24f alu is 16 bits wide and is capable of addi- tion, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. depending on the operation, the alu may affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array, or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. the pic24f cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 3.3.1 multiplier the alu contains a high-speed, 17-bit x 17-bit multiplier. it supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 16-bit x 16-bit signed 2. 16-bit x 16-bit unsigned 3. 16-bit signed x 5-bit (literal) unsigned 4. 16-bit unsigned x 16-bit unsigned 5. 16-bit unsigned x 5-bit (literal) unsigned 6. 16-bit unsigned x 16-bit signed 7. 8-bit unsigned x 8-bit unsigned register 3-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0, hsc r-1 u-0 u-0 ? ? ? ?ipl3 (1) r ? ? bit 7 bit 0 legend: c = clearable bit r = reserved bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit (1) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 reserved: read as ? 1 ? bit 1-0 unimplemented: read as ? 0 ? note 1: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level; see register 3-1 for bit description.
pic24fj256gb210 family ds39975a-page 42 ? 2010 microchip technology inc. 3.3.2 divider the divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn), and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algo- rithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.3.3 multi-bit shift support the pic24f alu supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. all multi-bit shift instructions only support register direct addressing for both the operand source and result destination. a full summary of instructions that use the shift operation is provided in table 3-2. table 3-2: instructions that use the si ngle bit and multi-bit shift operation instruction description asr arithmetic shift right source register by one or more bits. sl shift left source register by one or more bits. lsr logical shift right source register by one or more bits.
? 2010 microchip technology inc. ds39975a-page 43 pic24fj256gb210 family 4.0 memory organization as harvard architecture devices, pic24f micro- controllers feature separate program and data memory spaces and busses. this architecture also allows direct access of program memory from the data space during code execution. 4.1 program memory space the program address memory space of the pic24fj256gb210 family devices is 4m instructions. the space is addressable by a 24-bit value derived from either the 23-bit program counter (pc) during pro- gram execution, or from table operation or data space remapping, as described in section 4.3 ?interfacing program and data memory spaces? . user access to the program memory space is restricted to the lower half of the address range (000000h to 7fffffh). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. memory maps for the pic24fj256gb210 family of devices are shown in figure 4-1. figure 4-1: program space memory map for pic24fj256gb210 family devices 000000h 0000feh 000002h 000100h f8000eh f80010h fefffeh fffffeh 000004h 000200h 0001feh 000104h reset address devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj128gb2xx configuration memory space user memory space flash config words note: memory areas are not shown to scale. ff0000h f7fffeh f80000h device config registers 800000h 7ffffeh reserved 02ac00h 02abfeh unimplemented read ? 0 ? reset address device config registers user flash program memory (87k instructions) devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fj256gb2xx reserved flash config words unimplemented read ? 0 ? 015800h 0157feh user flash program memory (44k instructions)
pic24fj256gb210 family ds39975a-page 44 ? 2010 microchip technology inc. 4.1.1 program memory organization the program memory space is organized in word-addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address (figure 4-2). program memory addresses are always word-aligned on the lower word and addresses are incremented or decremented by two during code execution. this arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 4.1.2 hard memory vectors all pic24f devices reserve the addresses between 0x00000 and 0x000200 for hard coded program execu- tion vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user at 0x000000 with the actual address for the start of code at 0x000002. pic24f devices also have two interrupt vector tables, located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the many device interrupt sources to be handled by separate isrs. a more detailed discussion of the interrupt vector tables is provided in section 7.1 ?interrupt vector table? . 4.1.3 flash configuration words in pic24fj256gb210 family devices, the top four words of on-chip program memory are reserved for configuration information. on device reset, the configuration information is copied into the appropriate configuration register. the addresses of the flash configuration word for devices in the pic24fj256gb210 family are shown in table 4-1. their location in the memory map is shown with the other memory vectors in figure 4-1. the configuration words in program memory are a compact format. the actual configuration bits are mapped in several different regi sters in the configuration memory space. their order in the flash configuration words does not reflect a corresponding arrangement in the configuration space. additional details on the device configuration words are provided in section 26.1 ?configuration bits? . table 4-1: flash configuration words for pic24fj256gb210 family devices figure 4-2: program memory organization device program memory (words) configuration word addresses pic24fj128gb2xx 44,032 0x0157f8:0x0157fe pic24fj256gb2xx 87,552 0x02abf8:0x02abfe 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address)
? 2010 microchip technology inc. ds39975a-page 45 pic24fj256gb210 family 4.2 data memory space the pic24f core has a 16-bit wide data memory space, addressable as a single linear range. the data space is accessed using two address genera- tion units (agus), one each for read and write opera- tions. the data space memory map is shown in figure 4-3. the 16-bit wide data addresses in the data memory space point to bytes within the data space (ds). this gives a ds address range of 64 kbytes or 32k words. the lower 32 kbytes (0x0000 to 0x7fff) of ds is com- patible with the pic24f microcontrollers without eds. the upper 32 kbytes of data memory address space (0x8000 - 0xffff) are used as an eds window. the eds window is used to access all memory region implemented in eds, as shown in figure 4-4. the eds includes any additional internal data memory not accessible by the lower 32-kbyte data address space and any external memory through epmp. for more details on accessing internal extended data memory, refer to the ? pic24f family reference manual ?, section 45. ?data memory with extended data space (eds)? (ds39733). for more details on accessing external memory using epmp, refer to the ? pic24f family reference manual ?, section 42. ?enhanced parallel master port (epmp)? (ds39730) . in pic24f microcontrollers with eds, the program memory can also be read from eds. this is called program space visibility (psv). table 4-2 lists the total memory accessible by each of the devices in this family. the eds is organized as pages, with a single page called an eds page that equals the eds window (32 kbytes). a particular eds page is selected through the data space read register (dsrpag) or data space write register (dswpag). for psv, only the dsrpag register is used. the combination of the dsrpag register value and the 16-bit wide data address forms a 24-bit effective address (ea). for more information on eds, refer to section 4.3.3 ?reading data from program memory using eds? . note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 45. ?data memory with extended data space (eds)? (ds39733). the information in this data sheet supersedes the information in the frm. table 4-2: total memory accessible by the device devices internal ram external ram access using epmp program memory access using eds pic24fjxxxgb210 96 kbytes (30k + 66k (1) ) yes (up to 16 mb) yes pic24fjxxxgb206 96 kbytes (30k + 66k (1) ) yes (up to 64 kb) yes note 1: the internal ram above 30 kbytes can be accessed through the eds window.
pic24fj256gb210 family ds39975a-page 46 ? 2010 microchip technology inc. 4.2.1 data space width the data memory space is organized in byte-addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. figure 4-3: data space memory map fo r pic24fj256gb210 family devices (1) note 1: data memory areas are not shown to scale. 0000h 07feh fffeh lsb address lsb msb msb address 0001h 07ffh 1fffh ffffh 8001h 8000h 7fffh 0801h 0800h 2001h near 1ffeh sfr sfr space 2000h 7ffeh eds window space data space lower 32 kbytes data space eds page 0x1 eds page 0x2 eds page 0x3 (2 kb) eds page 0x4 eds page 0x200 eds page 0x300 eds page 0x1ff eds page 0x2ff eds page 0x3ff internal extended data ram(66 kbytes) program space visibility area to access lower word of program memory epmp memory space program space visibility area to access upper word of program memory upper 32 kbytes data space (32 kb) (32 kb) 30 kbytes data ram
? 2010 microchip technology inc. ds39975a-page 47 pic24fj256gb210 family 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcus and improve data space memory usage efficiency, the pic24f instruction set supports both word and byte operations. as a consequence of byte accessibility, all ea calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word, which contains the byte, using the lsb of any ea to deter- mine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. data byte writes only write to the corresponding side of the array or register which matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap will be generated. if the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. in either case, a trap is then executed, allow- ing the system and/or user to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the lsb. the most significant byte (msb) is not modified. a sign-extend instruction ( se ) is provided to allow users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, users can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 4.2.3 near data space the 8-kbyte area between 0000h and 1fffh is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. the remainder of the data space is indirectly addressable. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing with a 16-bit address field. 4.2.4 special function register (sfr) space the first 2 kbytes of the near data space, from 0000h to 07ffh, are primarily occupied with special function registers (sfrs). these are used by the pic24f core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they con- trol and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. a diagram of the sfr space, showing where the sfrs are actually implemented, is shown in table 4-3. each implemented area indicates a 32-byte region where at least one address is imple- mented as an sfr. a complete list of implemented sfrs, including their addresses, is shown in tables 4-4 throughtable 4-33. table 4-3: implemented regions of sfr data space sfr space address xx00 xx20 xx40 xx60 xx80 xxa0 xxc0 xxe0 000h core icn interrupts 100h timers capture compare 200h i 2 c? uart spi/uart spi/i 2 c spi uart i/o 300h adc/ctmu ? ? ? ? ? 400h ? ? ? ? usb ansel 500h ? ? ? ? ? ? ? ? 600h epmp rtc/comp crc ? pps ? 700h ? ? system nvm/pmd ? ? ? ? legend: ? = there are no implemented sfrs in this block
pic24fj256gb210 family ds39975a-page 48 ? 2010 microchip technology inc. table 4-4: cpu core registers map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit value register xxxx pcl 002e program counter low word register 0000 pch 0030 ? ? ? ? ? ? ? ? program counter register high byte 0000 dsrpag 0032 ? ? ? ? ? ? extended data space read page address register 0001 dswpag 0034 ? ? ? ? ? ? ? extended data space write page address register 0001 rcount 0036 repeat loop counter register xxxx sr 0042 ? ? ? ? ? ? ? dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? ? ? ? ? ? ? ? ? ?ipl3 r ? ? 0004 disicnt 0052 ? ? disable interrupts counter register xxxx tblpag 0054 ? ? ? ? ? ? ? ? table memory page address register 0000 legend: ? = unimplemented, read as ? 0 ?; r = reserved. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 49 pic24fj256gb210 family table 4-5: icn register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnpd1 0056 cn15pde cn14pde cn13pde cn12pde cn11pde cn10pde cn9pde cn8pde cn7pde cn6pde cn5pde cn4pde cn3pde cn2pde cn1pde cn0pde 0000 cnpd2 0058 cn31pde cn30pde cn29pde cn28pde cn27pde cn26pde cn25pde cn24pde cn23pde cn22pde cn21pde (1) cn20pde (1) cn19pde (1) cn18pde cn17pde cn16pde 0000 cnpd3 005a cn47pde (1) cn46pde (1) cn45pde (1) cn44pde (1) cn43pde (1) cn42pde (1) cn41pde (1) cn40pde (1) cn39pde (1) cn38pde (1) cn37pde (1) cn36pde (1) cn35pde (1) cn34pde (1) cn33pde (1) cn32pde 0000 cnpd4 005c cn63pde cn62pde cn61pde cn60pde cn59pde cn58pde cn57pde (1) cn56pde cn55pde cn54pde cn53pde cn52pde cn51pde cn50pde cn49pde cn48pde (1) 0000 cnpd5 005e cn79pde (1) cn78pde (1) cn77pde (1) cn76pde (1) cn75pde (1) cn74pde (1) cn73pde (1) ? cn71pde cn70pde (1) cn69pde cn68pde cn67pde (1) cn66pde (1) cn65pde cn64pde 0000 cnpd6 0060 ? ? ? ? ? ? ? ? ? ? ? cn84pde cn83pde cn82pde (1) cn81pde (1) cn80pde (1) 0000 cnen1 0062 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0064 cn31ie cn30ie cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn23ie cn22ie cn21ie (1) cn20ie (1) cn19ie (1) cn18ie cn17ie cn16ie 0000 cnen3 0066 cn47ie (1) cn46ie (1) cn45ie (1) cn44ie (1) cn43ie (1) cn42ie (1) cn41ie (1) cn40ie (1) cn39ie (1) cn38ie (1) cn37ie (1) cn36ie (1) cn35ie (1) cn34ie (1) cn33ie (1) cn32ie 0000 cnen4 0068 cn63ie cn62ie cn61ie cn60ie cn59ie cn58ie cn57ie (1) cn56ie cn55ie cn54ie cn53ie cn52ie cn51ie cn50ie cn49ie cn48ie (1) 0000 cnen5 006a cn79ie (1) cn78ie (1) cn77ie (1) cn76ie (1) cn75ie (1) cn74ie (1) cn73ie (1) ? cn71ie cn70ie (1) cn69ie cn68ie cn67ie (1) cn66ie (1) cn65ie cn64ie 0000 cnen6 006c ? ? ? ? ? ? ? ? ? ? ? cn84ie cn83ie cn82ie (1) cn81ie (1) cn80ie (1) 0000 cnpu1 006e cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 0070 cn31pue cn30pue cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue (1) cn20pue (1) cn19pue (1) cn18pue cn17pue cn16pue 0000 cnpu3 0072 cn47pue (1) cn46pue (1) cn45pue (1) cn44pue (1) cn43pue (1) cn42pue (1) cn41pue (1) cn40pue (1) cn39pue (1) cn38pue (1) cn37pue (1) cn36pue (1) cn35pue (1) cn34pue (1) cn33pue (1) cn32pue 0000 cnpu4 0074 cn63pue cn62pue cn61pue cn60pue cn59pue cn58pue cn57pue (1) cn56pue cn55pue cn54pue cn53pue cn52pue cn51pue cn50pue cn49pue cn48pue (1) 0000 cnpu5 0076 cn79pue (1) cn78pue (1) cn77pue (1) cn76pue (1) cn75pue (1) cn74pue (1) cn73pue (1) ? cn71pue cn70pue (1) cn69pue cn68pue cn67pue (1) cn66pue (1) cn65pue cn64pue 0000 cnpu6 0078 ? ? ? ? ? ? ? ? ? ? ? cn84pue cn83pue cn82pue (1) cn81pue (1) cn80pue (1) 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: unimplemented in 64-pin devices; read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 50 ? 2010 microchip technology inc. table 4-6: interrupt controller register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ? ? ? ? ? ? ? ? ? ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 ifs0 0084 ? ? ad1if u1txif u1rxif spi1if spf1if t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 u2txif u2rxif int2if t5if t4if oc4if oc3if ? ic8if ic7if ? int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0088 ? ? pmpif oc8if oc7if oc6if oc5if ic6if ic5if ic4if ic3if ? ? ?spi2ifspf2if 0000 ifs3 008a ?rtcif ? ? ? ? ? ? ? int4if int3if ? ? mi2c2if si2c2if ? 0000 ifs4 008c ? ?ctmuif ? ? ? ?lvdif ? ? ? ? crcif u2erif u1erif ? 0000 ifs5 008e ? ? ic9if oc9if spi3if spf3if u4txif u4rxif u4erif usb1if mi2c3if si2c3if u3txif u3rxif u3erif ? 0000 iec0 0094 ? ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie ? ic8ie ic7ie ? int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0098 ? ? pmpie oc8ie oc7ie oc6ie oc5ie ic6ie ic5ie ic4ie ic3ie ? ? ? spi2ie spf2ie 0000 iec3 009a ?rtcie ? ? ? ? ? ? ? int4ie int3ie ? ? mi2c2ie si2c2ie ? 0000 iec4 009c ? ?ctmuie ? ? ? ?lvdie ? ? ? ? crcie u2erie u1erie ? 0000 iec5 009e ? ? ic9ie oc9ie spi3ie spf3ie u4txie u4rxie u4erie usb1ie mi2c3ie si2c3ie u3txie u3rxie u3erie ? 0000 ipc0 00a4 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 4444 ipc1 00a6 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? 4440 ipc2 00a8 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 ? spf1ip2 spf1ip1 spf1ip0 ?t3ip2t3ip1t3ip0 4444 ipc3 00aa ? ? ? ? ? ? ? ? ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 0044 ipc4 00ac ? cnip2 cnip1 cnip0 ?cmip2cmip1cmip0 ? mi2c1ip2 mi2c1ip1 mi2c1ip0 ? si2c1ip2 si2c1ip1 si2c1ip0 4444 ipc5 00ae ? ic8ip2 ic8ip1 ic8ip0 ? ic7ip2 ic7ip1 ic7ip0 ? ? ? ? ? int1ip2 int1ip1 int1ip0 4404 ipc6 00b0 ? t4ip2 t4ip1 t4ip0 ? oc4ip2 oc4ip1 oc4ip0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? 4440 ipc7 00b2 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 ? int2ip2 int2ip1 int2ip0 ?t5ip2t5ip1t5ip0 4444 ipc8 00b4 ? ? ? ? ? ? ? ? ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 0044 ipc9 00b6 ? ic5ip2 ic5ip1 ic5ip0 ? ic4ip2 ic4ip1 ic4ip0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? 4440 ipc10 00b8 ? oc7ip2 oc7ip1 oc7ip0 ? oc6ip2 oc6ip1 oc6ip0 ? oc5ip2 oc5ip1 oc5ip0 ? ic6ip2 ic6ip1 ic6ip0 4444 ipc11 00ba ? ? ? ? ? ? ? ? ? pmpip2 pmpip1 pmpip0 ? oc8ip2 oc8ip1 oc8ip0 0044 ipc12 00bc ? ? ? ? ? mi2c2ip2 mi2c2ip1 mi2c2ip0 ? si2c2ip2 si2c2ip1 si2c2ip0 ? ? ? ? 0440 ipc13 00be ? ? ? ? ? int4ip2 int4ip1 int4ip0 ? int3ip2 int3ip1 int3ip0 ? ? ? ? 0440 ipc15 00c2 ? ? ? ? ? rtcip2 rtcip1 rtcip0 ? ? ? ? ? ? ? ? 0400 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 51 pic24fj256gb210 family ipc16 00c4 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? 4440 ipc18 00c8 ? ? ? ? ? ? ? ? ? ? ? ? ? lvdip2 lvdip1 lvdip0 0004 ipc19 00ca ? ? ? ? ? ? ? ? ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? 0040 ipc20 00cc ? u3txip2 u3txip1 u3txip0 ? u3rxip2 u3rxip1 u3rxip0 ? u3erip2 u3erip1 u3erip0 ? ? ? ? 4440 ipc21 00ce ? u4erip2 u4erip1 u4erip0 ? usb1ip2 usb1ip1 usb1ip0 ? mi2c3ip2 mi2c3ip1 mi2c3ip0 ? si2c3ip2 si2c3ip1 si2c3ip0 4444 ipc22 00d0 ? spi3ip2 spi3ip1 spi3ip0 ? spf3ip2 spf3ip1 spf3ip0 ? u4txip2 u4txip1 u4txip0 ? u4rxip2 u4rxip1 u4rxip0 4444 ipc23 00d2 ? ? ? ? ? ? ? ? ? ic9ip2 ic9ip1 ic9ip0 ? oc9ip2 oc9ip1 oc9ip0 0044 inttreg 00e0 cpuirq ?vhold ? ilr3 ilr2 ilr1 ilr0 ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 table 4-6: interrupt controller register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-7: timer register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 timer1 period register ffff t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) 0000 tmr3 010a timer3 register 0000 pr2 010c timer2 period register ffff pr3 010e timer3 period register ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 tmr4 0114 timer4 register 0000 tmr5hld 0116 timer5 holding register (for 32-bit operations only) 0000 tmr5 0118 timer5 register 0000 pr4 011a timer4 period register ffff pr5 011c timer5 period register ffff t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t45 ?tcs ? 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj256gb210 family ds39975a-page 52 ? 2010 microchip technology inc. table 4-8: input capture register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1con1 0140 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic1con2 0142 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic1buf 0144 input capture 1 buffer register 0000 ic1tmr 0146 input capture 1 timer value register xxxx ic2con1 0148 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2con2 014a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic2buf 014c input capture 2 buffer register 0000 ic2tmr 014e input capture 2 timer value register xxxx ic3con1 0150 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic3con2 0152 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic3buf 0154 input capture 3 buffer register 0000 ic3tmr 0156 input capture 3 timer value register xxxx ic4con1 0158 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic4con2 015a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic4buf 015c input capture 4 buffer register 0000 ic4tmr 015e input capture 4 timer value register xxxx ic5con1 0160 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic5con2 0162 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic5buf 0164 input capture 5 buffer register 0000 ic5tmr 0166 input capture 5 timer value register xxxx ic6con1 0168 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic6con2 016a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic6buf 016c input capture 6 buffer register 0000 ic6tmr 016e input capture 6 timer value register xxxx ic7con1 0170 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic7con2 0172 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic7buf 0174 input capture 7 buffer register 0000 ic7tmr 0176 input capture 7 timer value register xxxx ic8con1 0178 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic8con2 017a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic8buf 017c input capture 8 buffer register 0000 ic8tmr 017e input capture 8 timer value register xxxx ic9con1 0180 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic9con2 0182 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic9buf 0184 input capture 9 buffer register 0000 ic9tmr 0186 input capture 9 timer value register xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 53 pic24fj256gb210 family table 4-9: output compare register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1con1 0190 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc1con2 0192 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc1rs 0194 output compare 1 secondary register 0000 oc1r 0196 output compare 1 register 0000 oc1tmr 0198 output compare 1 timer value register xxxx oc2con1 019a ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc2con2 019c fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc2rs 019e output compare 2 secondary register 0000 oc2r 01a0 output compare 2 register 0000 oc2tmr 01a2 output compare 2 timer value register xxxx oc3con1 01a4 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc3con2 01a6 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc3rs 01a8 output compare 3 secondary register 0000 oc3r 01aa output compare 3 register 0000 oc3tmr 01ac output compare 3 timer value register xxxx oc4con1 01ae ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc4con2 01b0 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc4rs 01b2 output compare 4 secondary register 0000 oc4r 01b4 output compare 4 register 0000 oc4tmr 01b6 output compare 4 timer value register xxxx oc5con1 01b8 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt1 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc5con2 01ba fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc5rs 01bc output compare 5 secondary register 0000 oc5r 01be output compare 5 register 0000 oc5tmr 01c0 output compare 5 timer value register xxxx oc6con1 01c2 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc6con2 01c4 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc6rs 01c6 output compare 6 secondary register 0000 oc6r 01c8 output compare 6 register 0000 oc6tmr 01ca output compare 6 timer value register xxxx oc7con1 01cc ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc7con2 01ce fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc7rs 01d0 output compare 7 secondary register 0000 oc7r 01d2 output compare 7 register 0000 oc7tmr 01d4 output compare 7 timer value register xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj256gb210 family ds39975a-page 54 ? 2010 microchip technology inc. oc8con1 01d6 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc8con2 01d8 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc8rs 01da output compare 8 secondary register 0000 oc8r 01dc output compare 8 register 0000 oc8tmr 01de output compare 8 timer value register xxxx oc9con1 01e0 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc9con2 01e2 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc9rs 01e4 output compare 9 secondary register 0000 oc9r 01e6 output compare 9 register 0000 oc9tmr 01e8 output compare 9 timer value register xxxx table 4-9: output compare register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-10: i 2 c? register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? i2c1 receive register 0000 i2c1trn 0202 ? ? ? ? ? ? ? ? i2c1 transmit register 00ff i2c1brg 0204 ? ? ? ? ? ? ? i2c1 baud rate generator register 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? i2c1 address register 0000 i2c1msk 020c ? ? ? ? ? ? i2c1 address mask register 0000 i2c2rcv 0210 ? ? ? ? ? ? ? ? i2c2 receive register 0000 i2c2trn 0212 ? ? ? ? ? ? ? ? i2c2 transmit register 00ff i2c2brg 0214 ? ? ? ? ? ? ? i2c2 baud rate generator register 0000 i2c2con 0216 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c2stat 0218 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c2add 021a ? ? ? ? ? ? i2c2 address register 0000 i2c2msk 021c ? ? ? ? ? ? i2c2 address mask register 0000 i2c3rcv 0270 ? ? ? ? ? ? ? ? i2c3 receive register 0000 i2c3trn 0272 ? ? ? ? ? ? ? ? i2c3 transmit register 00ff i2c3brg 0274 ? ? ? ? ? ? ? i2c3 baud rate generator register 0000 i2c3con 0276 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c3stat 0278 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c3add 027a ? ? ? ? ? ? i2c3 address register 0000 i2c3msk 027c ? ? ? ? ? ? i2c3 address mask register 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 55 pic24fj256gb210 family table 4-11: uart register maps file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? uart1 transmit register xxxx u1rxreg 0226 ? ? ? ? ? ? ? uart1 receive register 0000 u1brg 0228 uart1 baud rate generator prescaler register 0000 u2mode 0230 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u2txreg 0234 ? ? ? ? ? ? ? uart2 transmit register xxxx u2rxreg 0236 ? ? ? ? ? ? ? uart2 receive register 0000 u2brg 0238 uart2 baud rate generator prescaler register 0000 u3mode 0250 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u3sta 0252 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u3txreg 0254 ? ? ? ? ? ? ? uart3 transmit register xxxx u3rxreg 0256 ? ? ? ? ? ? ? uart3 receive register 0000 u3brg 0258 uart3 baud rate generator prescaler register 0000 u4mode 02b0 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u4sta 02b2 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u4txreg 02b4 ? ? ? ? ? ? ? uart4 transmit register xxxx u4rxreg 02b6 ? ? ? ? ? ? ? uart4 receive register 0000 u4brg 02b8 uart4 baud rate generator prescaler register 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj256gb210 family ds39975a-page 56 ? 2010 microchip technology inc. table 4-12: spi register maps file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi1buf 0248 spi1 transmit and receive buffer 0000 spi2stat 0260 spien ? spisidl ? ? spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi2con1 0262 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi2con2 0264 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi2buf 0268 spi2 transmit and receive buffer 0000 spi3stat 0280 spien ? spisidl ? ? spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi3con1 0282 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi3con2 0284 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi3buf 0288 spi3 transmit and receive buffer 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-13: porta register map (1) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit 1 bit 0 all resets trisa 02c0 trisa15 trisa14 ? ? ? trisa10 trisa9 ? trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 c6ff porta 02c2 ra15 ra14 ? ? ? ra10 ra9 ? ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 lata15 lata14 ? ? ? lata10 lata9 ? lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 oda15 oda14 ? ? ?oda10oda9 ? oda7 oda6 oda5 oda4 oda3 oda2 oda1 oda0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: porta and all associated bits are unimplemented on 64-pin devices and read as ? 0 ?. bits are available on 100-pin devices only, unless otherwise noted. table 4-14: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx odcb 02ce odb15 odb14 odb13 odb12 odb11 odb10 odb9 odb8 odb7 odb6 odb5 odb4 odb3 odb2 odb1 odb0 0000 legend: reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 57 pic24fj256gb210 family table 4-15: portc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 (1) bit 3 (1) bit 2 (1) bit 1 (1) bit 0 all resets trisc 02d0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? f01e portc 02d2 rc15 (2,3) rc14 rc13 rc12 (2) ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? xxxx latc 02d4 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? xxxx odcc 02d6 odc15 odc14 odc13 odc12 ? ? ? ? ? ? ? odc4 odc3 odc2 odc1 ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?. 2: rc12 and rc15 are only available when the primary oscillator is disabled or when ec mode is selected (poscmd<1:0> configuration bits = 11 or 00 ); otherwise read as ? 0 ?. 3: rc15 is only available when the poscmd<1:0> configuration bits = 11 or 00 and the osciofn configuration bit = 1 . table 4-16: portd register map file name addr bit 15 (1) bit 14 (1) bit 13 (1) bit 12 (1) bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisd 02d8 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 ffff portd 02da rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx latd 02dc latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx odcd 02de odd15 odd14 odd13 odd12 odd11 odd10 odd9 odd8 odd7 odd6 odd5 odd4 odd3 odd2 odd1 odd0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?. table 4-17: porte register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 (1) bit 8 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trise 02e0 ? ? ? ? ? ? trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 03ff porte 02e2 ? ? ? ? ? ? re9re8re7re6re5re4re3re2re1re0 xxxx late 02e4 ? ? ? ? ? ? late9 late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx odce 02e6 ? ? ? ? ? ? ode9ode8ode7ode6ode5ode4ode3ode2ode1ode0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 58 ? 2010 microchip technology inc. table 4-18: portf register map file name addr bit 15 bit 14 bit 13 (1) bit 12 (1) bit 11 bit 10 bit 9 bit 8 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 (1) bit 1 bit 0 all resets trisf 02e8 ? ?trisf13trisf12 ? ? ?trisf8trisf7 ? trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 31bf portf 02ea ? ? rf13 rf12 ? ? ?rf8rf7 ? rf5rf4rf3rf2rf1rf0 xxxx latf 02ec ? ? latf13 latf12 ? ? ? latf8 latf7 ? latf5 latf4 latf3 latf2 latf1 latf0 xxxx odcf 02ee ? ?odf13odf12 ? ? ? odf8 odf7 ? odf5 odf4 odf3 odf2 odf1 odf0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?. table 4-19: portg register map file name addr bit 15 (1) bit 14 (1) bit 13 (1) bit 12 (1) bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (1) bit 0 (1) all resets trisg 02f0 trisg15 trisg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 f3cf portg 02f2 rg15 rg14 rg13 rg12 ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 xxxx latg 02f4 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 xxxx odcg 02f6 odg15 odg14 odg13 odg12 ? ? odg9 odg8 odg7 odg6 ? ? odg3 odg2 odg1 odg0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. reset values shown are for 100-pin devices. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?. table 4-20: pad config uration register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets padcfg1 02fc ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtsecsel pmpttl 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 59 pic24fj256gb210 family table 4-21: adc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1buff 031e adc data buffer 15 xxxx adc1buf10 0340 adc data buffer 16 xxxx adc1buf11 0342 adc data buffer 17 xxxx adc1buf12 0344 adc data buffer 18 xxxx adc1buf13 0346 adc data buffer 19 xxxx adc1buf14 0348 adc data buffer 20 xxxx adc1buf15 034a adc data buffer21 xxxx adc1buf16 034c adc data buffer 22 xxxx adc1buf17 034e adc data buffer 23 xxxx adc1buf18 0350 adc data buffer 24 xxxx adc1buf19 0352 adc data buffer 25 xxxx adc1buf1a 0354 adc data buffer 26 xxxx adc1buf1b 0356 adc data buffer 27 xxxx adc1buf1c 0358 adc data buffer 28 xxxx adc1buf1d 035a adc data buffer 29 xxxx adc1buf1e 035c adc data buffer 30 xxxx adc1buf1f 035e adc data buffer 31 xxxx legend: ? = unimplemented, read as ? 0 ?, r = reserved, maintain as ? 0 ?. reset values are shown in hexadecimal. note 1: unimplemented in 64-pin devices, read as ? 0 ?
pic24fj256gb210 family ds39975a-page 60 ? 2010 microchip technology inc. ad1con1 0320 adon ? adsidl ? ? ? form1 form0 ssrc2 ssrc1 ssrc0 ? ? asam samp done 0000 ad1con2 0322 vcfg2 vcfg1 vcfg0 r ? cscna ? ? bufs smpi4 smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0324 adrc r r samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs 0328 ch0nb ? ? ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na ? ? ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1cssh 032e ? ? ? ? cssl27 cssl26 cssl25 cssl24 cssl23 (1) cssl22 (1) cssl21 (1) cssl20 (1) cssl19 (1) cssl18 (1) cssl17 (1) cssl16 (1) 0000 ad1cssl 0330 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 table 4-21: adc register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?, r = reserved, maintain as ? 0 ?. reset values are shown in hexadecimal. note 1: unimplemented in 64-pin devices, read as ? 0 ? table 4-22: ctmu register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ctmucon 033c ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig edg2pol edg2sel1 edg2sel0 edg1pol edg1sel1 edg1sel0 edg2stat edg1stat 0000 ctmuicon 033e itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 ? ? ? ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 61 pic24fj256gb210 family table 4-23: usb otg register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1otgir (2) 0480 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 u1otgie (2) 0482 ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 u1otgstat 2) 0484 ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 u1otgcon (2) 0486 ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 u1pwrc 0488 ? ? ? ? ? ? ? ?uactpnd ? ?uslpgrd ? ? ususpnd usbpwr 0000 u1ir 048a (1) ? ? ? ? ? ? ? ?stallif ? resumeif idleif trnif sofif uerrif urstif 0000 ? ? ? ? ? ? ? ? stallif attachif (1) resumeif idleif trnif sofif uerrif detachif (1) 0000 u1ie 048c (1) ? ? ? ? ? ? ? ? stallie ? resumeie idleie trnie sofie uerrie urstie 0000 ? ? ? ? ? ? ? ? stallie attachie (1) resumeie idleie trnie sofie uerrie detachie (1) 0000 u1eir 048e (1) ? ? ? ? ? ? ? ?btsef ? dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 ? ? ? ? ? ? ? ?btsef ? dmaef btoef dfn8ef crc16ef eofef (1) pidef 0000 u1eie 0490 (1) ? ? ? ? ? ? ? ?btsee ? dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 ? ? ? ? ? ? ? ?btsee ? dmaee btoee dfn8ee crc16ee eofee (1) pidee 0000 u1stat 0492 ? ? ? ? ? ? ? ? endpt3 endpt2 endpt1 endpt0 dir ppbi ? ? 0000 u1con 0494 (1) ? ? ? ? ? ? ? ? ? se0 pktdis ? hosten resume ppbrst usben 0000 ? ? ? ? ? ? ? ?jstate (1) se0 tokbusy usbrst hosten resume ppbrst sofen (1) 0000 u1addr 0496 ? ? ? ? ? ? ? ?lspden (1) usb device address (devaddr) register 0000 u1bdtp1 0498 ? ? ? ? ? ? ? ? buffer descriptor table base address register ? 0000 u1frml 049a ? ? ? ? ? ? ? ? frame count register low byte 0000 u1frmh 049c ? ? ? ? ? ? ? ? ? ? ? ? ? frame count register high byte 0000 u1tok (2) 049e ? ? ? ? ? ? ? ? pid3 pid2 pid1 pid0 ep3 ep2 ep1 ep0 0000 u1sof (2) 04a0 ? ? ? ? ? ? ? ? start-of-frame count register 0000 u1cnfg1 04a6 ? ? ? ? ? ? ? ?uteyeuoemon ? usbsidl ? ? ppb1 ppb0 0000 u1cnfg2 04a8 ? ? ? ? ? ? ? ? ? ? uvcmpsel puvbus exti2cen uvbusdis uvcmpdis utrdis 0000 u1ep0 04aa ? ? ? ? ? ? ? ?lspd (1) retrydis (1) ? epcondis eprxen eptxen epstall ephshk 0000 u1ep1 04ac ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep2 04ae ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep3 04b0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep4 04b2 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep5 04b4 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep6 04b6 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep7 04b8 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep8 04ba ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep9 04bc ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: alternate register or bit definitions when the module is operating in host mode. 2: this register is available in host mode only.
pic24fj256gb210 family ds39975a-page 62 ? 2010 microchip technology inc. u1ep10 04be ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep11 04c0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep12 04c2 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep13 04c4 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep14 04c6 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1ep15 04c8 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 u1pwmrrs 04cc usb power supply pwm duty cycle register usb power supply pwm period register 0000 u1pwmcon 04ce pwmen ? ? ? ? ? pwmpol cnten ? ? ? ? ? ? ? ? 0000 table 4-23: usb otg register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: alternate register or bit definitions when the module is operating in host mode. 2: this register is available in host mode only. table 4-24: ancfg register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ancfg 04de ? ? ? ? ? ? ? ? ? ? ? ? ? vbg6en vbg2en vbgen 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-25: ansel register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets (2) ansa (1) 04e0 ? ? ? ? ? ansa10 (1) ansa9 (1) ? ansa7 (1) ansa6 (1) ? ? ? ? ? ? 06c0 ansb 04e2 ansb15 ansb14 ansb13 ansb12 ansb11 ansb10 ansb9 ansb8 ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 ffff ansc 04e4 ? ansc14 ansc13 ? ? ? ? ? ? ? ?ansc4 (1) ? ? ? ? 6010 ansd 04e6 ? ? ? ? ? ? ? ? ansd7 ansd6 ? ? ? ? ? ? 00c0 anse (1) 04e8 ? ? ? ? ? ?anse9 (1) ? ? ? ? ? ? ? ? ? 0200 ansf 04ea ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ansf0 0001 ansg 04ec ? ? ? ? ? ? ansg9 ansg8 ansg7 ansg6 ? ? ? ? ? ? 03c0 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: unimplemented in 64-pin devices, read as ? 0 ?. 2: reset values are valid for 100-pin devices only.
? 2010 microchip technology inc. ds39975a-page 63 pic24fj256gb210 family table 4-26: enhanced parallel master/slave port register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmcon1 0600 pmpen ? psidl adrmux1 adrmux0 ? mode1 mode0 csf1 csf0 alp almode ? buskeep irqm1 irqm0 0000 pmcon2 0602 busy ? error timeout r r r r raddr23 raddr22 raddr21 raddr20 raddr19 raddr18 raddr17 raddr16 0000 pmcon3 0604 ptwren ptrden ptbe1en ptbe0en ? awaitm1 awaitm0 awaite ?pten22 (1) pten21 (1) pten20 (1) pten19 (1) pten18 (1) pten17 (1) pten16 (1) 0000 pmcon4 0606 pten15 pten14 pten13 pten12 pten11 pten10 pten9 pten8 pten7 pten6 pten5 pten4 pten3 pten2 pten1 pten0 0000 pmcs1cf 0608 csdis csp cspten bep ? wrsp rdsp sm ackp ptsz1 ptsz0 ? ? ? ? ? 0000 pmcs1bs 060a base23 base22 base21 base20 base19 base18 base17 base16 base15 ? ? ?base11 ? ? ? 0200 pmcs1md 060c ackm1 ackm0 r r r ? ? ? dwaitb1 dwaitb0 dwaitm3 dwaitm2 dwaitm1 dwaitm0 dwaite1 dwaite0 0000 pmcs2cf 060e csdis csp cspten bep ? wrsp rdsp sm ackp ptsz1 ptsz0 ? ? ? ? ? 0000 pmcs2bs 0610 base23 base22 base21 base20 base19 base18 base17 base16 base15 ? ? ?base11 ? ? ? 0600 pmcs2md 0612 ackm1 ackm0 r r r ? ? ? dwaitb1 dwaitb0 dwaitm3 dwaitm2 dwaitm1 dwaitm0 dwaite1 dwaite0 0000 pmdout1 0614 epmp data out register 1<15:8> epmp data out register 1<7:0> xxxx pmdout2 0616 epmp data out register 2<15:8> epmp data out register 2<7:0> xxxx pmdin1 0618 epmp data in register 1<15:8> epmp data in register 1<7:0> xxxx pmdin2 061a epmp data in register 2<15:8> epmp data in register 2<7:0> xxxx pmstat 061c ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 008f legend: ? = unimplemented, read as ? 0 ?, r = reserved. reset values are shown in hexadecimal. note 1: unimplemented in 64-pin devices, read as ? 0 ?. table 4-27: real-time clock and calendar register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alarm value register window based on alrmptr<1:0> xxxx alcfgrpt 0622 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 0000 rtcval 0624 rtcc value register window based on rtcptr<1:0> xxxx rcfgcal 0626 rtcen ? rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 (note 1) legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the status of the rcfgcal register on por is ? 0000 ? and on other resets is unchanged.
pic24fj256gb210 family ds39975a-page 64 ? 2010 microchip technology inc. table 4-28: comparators register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmstat 0630 cmidl ? ? ? c3evt c2evt c1evt ? ? ? ? ? c3out c2out c1out 0000 cvrcon 0632 ? ? ? ? ? cvrefp cvrefm1 cvrefm0 cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 cm1con 0634 con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm2con 0636 con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm3con 0638 con coe cpol ? ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-29: crc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets crccon1 0640 crcen ? csidl vword4 vword3 vword2 vword1 vword0 crcful crcmpt crcisel crcgo lendian ? ? ? 0040 crccon2 0642 ? ? ? dwidth4 dwidth3 dwidth2 dwidth1 dwidth0 ? ? ? plen4 plen3 plen2 plen1 plen0 0000 crcxorl 0644 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 ? 0000 crcxorh 0646 x31 x30 x29 x28 x27 x26 x25 x24 x23 x22 x21 x20 x19 x18 x17 x16 0000 crcdatl 0648 crc data input register low 0000 crcdath 064a crc data input register high 0000 crcwdatl 064c crc result register low 0000 crcwdath 064e crc result register high 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2010 microchip technology inc. ds39975a-page 65 pic24fj256gb210 family table 4-30: peripheral pin select register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 ? ? int1r5 int1r4 int1r3 int1r2 int1r1 int1r0 ? ? ? ? ? ? ? ? 3f00 rpinr1 0682 ? ? int3r5 int3r4 int3r3 int3r2 int3r1 int3r0 ? ? int2r5 int2r4 int2r3 int2r2 int2r1 int2r0 3f3f rpinr2 0684 ? ? ? ? ? ? ? ? ? ? int4r5 int4r4 int4r3 int4r2 int4r1 int4r0 003f rpinr3 0686 ? ? t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 ? ? t2ckr5t2ckr4t2ckr3t2ckr2t2ckr1t2ckr0 3f3f rpinr4 0688 ? ? t5ckr5 t5ckr4 t5ckr3 t5ckr2 t5ckr1 t5ckr0 ? ? t4ckr5t4ckr4t4ckr3t4ckr2t4ckr1t4ckr0 3f3f rpinr7 068e ? ? ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 ? ? ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 3f3f rpinr8 0690 ? ? ic4r5 ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 ? ? ic3r5 ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 3f3f rpinr9 0692 ? ? ic6r5 ic6r4 ic6r3 ic6r2 ic6r1 ic6r0 ? ? ic5r5 ic5r4 ic5r3 ic5r2 ic5r1 ic5r0 3f3f rpinr10 0694 ? ? ic8r5 ic8r4 ic8r3 ic8r2 ic8r1 ic8r0 ? ? ic7r5 ic7r4 ic7r3 ic7r2 ic7r1 ic7r0 3f3f rpinr11 0696 ? ? ocfbr5 ocfbr4 ocfbr3 ocfbr2 ocfbr1 ocfbr0 ? ? ocfar5ocfar4ocfar3ocfar2ocfar1ocfar0 3f3f rpinr15 069e ? ? ic9r5 ic9r4 ic9r3 ic9r2 ic9r1 ic9r0 ? ? ? ? ? ? ? ? 3f00 rpinr17 06a2 ? ? u3rxr5 u3rxr4 u3rxr3 u3rxr2 u3rxr1 u3rxr0 ? ? ? ? ? ? ? ? 3f00 rpinr18 06a4 ? ? u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 ? ? u1rxr5u1rxr4u1rxr3u1rxr2u1rxr1u1rxr0 3f3f rpinr19 06a6 ? ? u2ctsr5 u2ctsr4 u2ctsr3 u2ctsr2 u2ctsr1 u2ctsr0 ? ? u2rxr5u2rxr4u2rxr3u2rxr2u2rxr1u2rxr0 3f3f rpinr20 06a8 ? ? sck1r5 sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 ? ? sdi1r5sdi1r4sdi1r3sdi1r2sdi1r1sdi1r0 3f3f rpinr21 06aa ? ? u3ctsr5 u3ctsr4 u3ctsr3 u3ctsr2 u3ctsr1 u3ctsr0 ? ? ss1r5 ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 3f3f rpinr22 06ac ? ? sck2r5 sck2r4 sck2r3 sck2r2 sck2r1 sck2r0 ? ? sdi2r5sdi2r4sdi2r3sdi2r2sdi2r1sdi2r0 3f3f rpinr23 06ae ? ? ? ? ? ? ? ? ? ? ss2r5 ss2r4 ss2r3 ss2r2 ss2r1 ss2r0 003f rpinr27 06b6 ? ? u4ctsr5 u4ctsr4 u4ctsr3 u4ctsr2 u4ctsr1 u4ctsr0 ? ? u4rxr5u4rxr4u4rxr3u4rxr2u4rxr1u4rxr0 3f3f rpinr28 06b8 ? ? sck3r5 sck3r4 sck3r3 sck3r2 sck3r1 sck3r0 ? ? sdi3r5sdi3r4sdi3r3sdi3r2sdi3r1sdi3r0 3f3f rpinr29 06ba ? ? ? ? ? ? ? ? ? ? ss3r5 ss3r4 ss3r3 ss3r2 ss3r1 ss3r0 003f legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 66 ? 2010 microchip technology inc. rpor0 06c0 ? ? rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 ? ? rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 0000 rpor1 06c2 ? ? rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 ? ? rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 0000 rpor2 06c4 ? ?rp5r5 (1) rp5r4 (1) rp5r3 (1) rp5r2 (1) rp5r1 (1) rp5r0 (1) ? ? rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 0000 rpor3 06c6 ? ? rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 ? ? rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 0000 rpor4 06c8 ? ? rp9r5 rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 ? ? rp8r5 rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 0000 rpor5 06ca ? ? rp11r5 rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 ? ? rp10r5 rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 0000 rpor6 06cc ? ? rp13r5 rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 ? ? rp12r5 rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 0000 rpor7 06ce ? ? rp15r5 (1) rp15r4 (1) rp15r3 (1) rp15r2 (1) rp15r1 (1) rp15r0 (1) ? ? rp14r5 rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 0000 rpor8 06d0 ? ? rp17r5 rp17r4 rp17r3 rp17r2 rp17r1 rp17r0 ? ? rp16r5 rp16r4 rp16r3 rp16r2 rp16r1 rp16r0 0000 rpor9 06d2 ? ? rp19r5 rp19r4 rp19r3 rp19r2 rp19r1 rp19r0 ? ? rp18r5 rp18r4 rp18r3 rp18r2 rp18r1 rp18r0 0000 rpor10 06d4 ? ? rp21r5 rp21r4 rp21r3 rp21r2 rp21r1 rp21r0 ? ? rp20r5 rp20r4 rp20r3 rp20r2 rp20r1 rp20r0 0000 rpor11 06d6 ? ? rp23r5 rp23r4 rp23r3 rp23r2 rp23r1 rp23r0 ? ? rp22r5 rp22r4 rp22r3 rp22r2 rp22r1 rp22r0 0000 rpor12 06d8 ? ? rp25r5 rp25r4 rp25r3 rp25r2 rp25r1 rp25r0 ? ? rp24r5 rp24r4 rp24r3 rp24r2 rp24r1 rp24r0 0000 rpor13 06da ? ? rp27r5 rp27r4 rp27r3 rp27r2 rp27r1 rp27r0 ? ? rp26r5 rp26r4 rp26r3 rp26r2 rp26r1 rp26r0 0000 rpor14 06dc ? ? rp29r5 rp29r4 rp29r3 rp29r2 rp29r1 rp29r0 ? ? rp28r5 rp28r4 rp28r3 rp28r2 rp28r1 rp28r0 0000 rpor15 (1) 06de ? ? rp31r5 (1) rp31r4 (1) rp31r3 (1) rp31r2 (1) rp31r1 (1) rp31r0 (1) ? ? rp30r5 (1) rp30r4 (1) rp30r3 (1) rp30r2 (1) rp30r1 (1) rp30r0 (1) 0000 table 4-30: peripheral pin select register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: bits are unimplemented in 64-pin devices; read as ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 67 pic24fj256gb210 family table 4-31: system register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr ? ? ? ? cm vregs extr swr swdten wdto sleep idle bor por note 1 osccon 0742 ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 clklock iolock lock ? cf poscen soscen oswen note 2 clkdiv 0744 roi doze2 doze1 doze0 dozen rcdiv2 rcdiv1 rcdiv0 cpdiv1 cpdiv0 pllen r ? ? ? ? 0100 osctun 0748 ? ? ? ? ? ? ? ? ? ? tun5 tun4 tun3 tun2 tun1 tun0 0000 refocon 074e roen ? rosslp rosel rodiv3 rodiv2 rodiv1 rodiv0 ? ? ? ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?, r = reserved. reset values are shown in hexadecimal. note 1: the reset value of the rcon register is dependent on the type of reset event. see section 6.0 ?resets? for more information. 2: the reset value of the osccon register is dependent on both the type of reset event and the device configuration. see section 8.0 ?oscillator configuration? for more information. table 4-32: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? ? ?erase ? ? nvmop3 nvmop2 nvmop1 nvmop0 0000 (1) nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey register<7:0> 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 4-33: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t5md t4md t3md t2md t1md ? ? ? i2c1md u2md u1md spi2md spi1md ? ? adc1md 0000 pmd2 0772 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 pmd3 0774 ? ? ? ? ? cmpmd rtccmd pmpmd crcmd ? ? ? u3md i2c3md i2c2md ? 0000 pmd4 0776 ? ? ? ? ? ? ? ? ? upwmmd u4md ? refomd ctmumd lvdmd usb1md 0000 pmd5 0778 ? ? ? ? ? ? ?ic9md ? ? ? ? ? ? ?oc9md 0000 pmd6 077a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?spi3md 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fj256gb210 family ds39975a-page 68 ? 2010 microchip technology inc. 4.2.5 extended data space (eds) the enhancement of the data space in pic24fj256gb210 family devices has been accomplished by a new technique, called the extended data space (eds). the eds includes any additional internal extended data memory not accessible by the lower 32 kbytes of data address space, any external memory through epmp and the program space visibility (psv). the extended data space is always accessed through the eds window, which is the upper half of data space. the entire extended data space is organized into eds pages, each having 32 kbytes of data. mapping of the eds page into the eds window is done by using the data space read register (dsrpag<9:0>) for read operations and data space write register (dswpag<8:0>) for write operations. figure 4-4 displays the entire eds space. figure 4-4: extended data space note: accessing page 0 in the eds window will generate an address error trap as page 0 is the base data memory (data locations, 0x0800 to 0x7fff, in the lower data space). 0x0000 extended sram (66 kb) special registers 30 kb data 32 kb eds window memory 0x8000 program memory dsxpag = 0x001 dsxpag = 0x003 dsx pag = 0x1ff dsrpag = 0x200 dsrpag = 0x3ff function 0x008000 0x00fffe 0x000000 0x7f8001 0xfffffe 0x007ffe 0x7fffff internal program space 0x0800 0xfffe eds space epmp memory space 0x018000 0x0187fe extended memory internal extended memory external memory access using epmp external memory access using epmp 0xff8000 dsrpag = 0x2ff 0x7f8000 0x7ffffe access program space access program space access dsrpag = 0x300 0x000001 0x007fff program space access 0x01fffe 0x018800
? 2010 microchip technology inc. ds39975a-page 69 pic24fj256gb210 family 4.2.5.1 data read from eds space in order to read the data from the eds space, first, an address pointer is set up by loading the required eds page number into the dsrpag register and assigning the offset address to one of the w registers. once the above assignment is done, the eds window is enabled by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed eds location can be read. figure 4-5 illustrates how the eds space address is generated for read operations. figure 4-5: eds address ge neration for read operations when the most significant bit (msb) of ea is ? 1 ? and dsrpag<9> = 0 , the lower 9 bits of dsrpag are con- catenated to the lower 15 bits of ea to form a 24-bit eds space address for read operations. example 4-1 shows how to read a byte, word and double-word from eds. example 4-1: eds read code in assembly dsrpag reg select wn 9 8 15 bits 9 bits 24-bit ea wn<0> is byte select 0 = extended sram and epmp 1 0 note: all read operations from eds space have an overhead of one instruction cycle. therefore, a minimum of two instruction cycles is required to complete an eds read. eds reads under the repeat instruction; the first two accesses take three cycles and the subsequent accesses take one cycle. ; set the eds page from where the data to be read mov #0x0002 , w0 mov w0 , dsrpag ;page 2 is selected for read mov #0x0800 , w1 ;select the location (0x800) to be read bset w1 , #15 ;set the msb of the base address, enable eds mode ;read a byte from the selected location mov.b [w1++] , w2 ;read low byte mov.b [w1++] , w3 ;read high byte ;read a word from the selected location mov [w1] , w2 ; ;read double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3
pic24fj256gb210 family ds39975a-page 70 ? 2010 microchip technology inc. 4.2.5.2 data write into eds space in order to write data to eds space, such as in eds reads, an address pointer is set up by loading the required eds page number into the dswpag register and assigning the offset address to one of the w regis- ters. once the above assignment is done, then the eds window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written. figure 4-2 illustrates how the eds space address is generated for write operations. figure 4-6: eds address gene ration for write operations when the msb of ea is ? 1 ?, the lower 9 bits of dswpag are concatenated to the lower 15 bits of ea to form a 24-bit eds address for write operations. example 4-2 shows how to write a byte, word and double-word to eds. example 4-2: eds write code in assembly dswpag reg select wn 8 15 bits 9 bits 24-bit ea wn<0> is byte select 1 0 ; set the eds page where the data to be written mov #0x0002 , w0 mov w0 , dswpag ;page 2 is selected for write mov #0x0800 , w1 ;select the location (0x800) to be written bset w1 , #15 ;set the msb of the base address, enable eds mode ;write a byte to the selected location mov #0x00a5 , w2 mov #0x003c , w3 mov.b w2 , [w1++] ;write low byte mov.b w3 , [w1++] ;write high byte ;write a word to the selected location mov #0x1234 , w2 ; mov w2 , [w1] ; ;write a double - word to the selected location mov #0x1122 , w2 mov #0x4455 , w3 mov.d w2 , [w1] ;2 eds writes
? 2010 microchip technology inc. ds39975a-page 71 pic24fj256gb210 family the page registers (dsrpag/dswpag) do not update automatically while crossing a page boundary when the rollover happens, from 0xffff to 0x8000. while developing code in assembly, care must be taken to update the page registers when an address pointer crosses the page boundary. the ?c? compiler keeps track of the addressing and increments or decrements the page registers accordingly while accessing contiguous data memory locations. table 4-34: eds memory address with different pages and addresses note 1: all write operations to eds are executed in a single cycle. 2: use of a read/modify/write operation on any eds location under a repeat instruction is not supported. for example: bclr, bsw, btg, rlc f, rlnc f, rrc f, rrnc f, add f, sub f, subr f, and f, ior f, xor f, asr f, asl f . 3: use the dsrpag register while performing a read/modify/write operation. dsrpag (data space read register) dswpag (data space write register) source/destination address while indirect addressing 24-bit ea pointing to eds comment x (1) x (1) 0x0000 to 0x1fff 0x000000 to 0x001fff near data space (2) 0x2000 to 0x7fff 0x002000 to 0x007fff 0x001 0x001 0x8000 to 0xffff 0x008000 to 0x00fffe 32 kbytes on each page 0x002 0x002 0x010000 to 0x017ffe 0x003 0x003 0x018000 to 0x0187fe only 2 kbytes of extended sram on this page 0x004 0x004 0x018800 to 0x027ffe epmp memory space ? ? ? ? ? ? ? ? ? 0x1ff 0x1ff 0xff8000 to 0xfffffe 0x000 0x000 invalid address address error trap (3) note 1: if the source/destination address is below 0x8000, the dsrpag and dswpag registers are not considered. 2: this data space can also be accessed by direct addressing. 3: when the source/destination address is above 0x8000 and dsrpag/dswpag is ? 0 ?, an address error trap will occur.
pic24fj256gb210 family ds39975a-page 72 ? 2010 microchip technology inc. 4.2.6 software stack apart from its use as a working register, the w15 register in pic24f devices is also used as a software stack pointer (ssp). the pointer always points to the first available free word and grows from lower to higher addresses. it pre-decrements for stack pops and post-increments for stack pushes, as shown in figure 4-7. note that for a pc push during any call instruction, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit value register (splim), associ- ated with the stack pointer, sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? as all stack operations must be word-aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim reg- ister are equal, and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in ram, initialize the splim with the value, 1ffeh. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0800h. this prevents the stack from interfering with the sfr space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 4-7: call stack frame 4.3 interfacing program and data memory spaces the pic24f architecture uses a 24-bit wide program space and 16-bit wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the pic24f architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this makes the method ideal for accessing data tables that need to be updated from time to time. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. it can only access the least significant word of the program word. 4.3.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table memory page address register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the msbs of tblpag are used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 10-bit extended data space read register (dsrpag) is used to define a 16k word page in the program space. when the most significant bit (msb) of the ea is ? 1 ?, and the msb (bit 9) of dsrpag is ? 1 ?, the lower 8 bits of dsrpag are con- catenated with the lower 15 bits of the ea to form a 23-bit program space address. the dsrpag<8> bit decides whether the lower word (when bit is ? 0 ?) or the higher word (when bit is ? 1 ?) of program memory is mapped. unlike table operations, this strictly limits remapping operations to the user memory area. table 4-35 and figure 4-8 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, whereas d<15:0> refers to a data space word. note: a pc push during exception processing will concatenate the srl register to the msb of the pc prior to the push. < free word > pc<15:0> 000000000 0 15 w15 ( before call ) w15 ( after call ) stack grows towards higher address 0000h pc<22:16> pop : [--w15] push : [w15++]
? 2010 microchip technology inc. ds39975a-page 73 pic24fj256gb210 family table 4-35: program space address construction figure 4-8: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 dsrpag<7:0> (2) data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calculating the program space address. bit 15 of the address is dsrpag<0>. 2: dsrpag<9> is always ? 1 ? in this case. dsrpag<8> decides whether the lower word or higher word of program memory is read. when dsrpag<8> is ? 0 ?, the lower word is read and when it is ? 1 ?, the higher word is read. 0 program counter 23 bits 1 dsrpag<7:0> 8 bits ea 15 bits program counter select tblpag 8 bits ea 16 bits byte select 0 0 1 / 0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1 / 0 1 / 0 note 1: dsrpag<8> acts as word select. dsrpag<9> should always be ? 1 ? to map program memory to data memory. 2: the instructions, tblrdh/tblwth/tblrdl/tblwtl , decide if the higher or lower word of program memory is accessed. tblrdh/tblwth instructions access the higher word and tblrdl/tblwtl instructions access the lower word. table read operations are permitted in the configuration memory space. 1-bit
pic24fj256gb210 family ds39975a-page 74 ? 2010 microchip technology inc. 4.3.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which contains the least significant data word, and tblrdh and tblwth access the space which contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. 1. tblrdl (table read low): in word mode, it maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. 2. tblrdh (table read high): in word mode, it maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom? byte, will always be ? 0 ?. in byte mode, it maps the upper or lower byte of the program word to d<7:0> of the data address, as above. note that the data will always be ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are described in section 5.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table memory page address register (tblpag). tblpag covers the entire program memory space of the device, including user and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-9: accessing program memory with table instructions note: only table read operations will execute in the configuration memory space, where device ids are located. table write operations are not allowed. 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 000000h 800000h 020000h 030000h program space data ea<15:0> the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area.
? 2010 microchip technology inc. ds39975a-page 75 pic24fj256gb210 family 4.3.3 reading data from program memory using eds the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., tblrdl/h ). program space access through the data space occurs when the msb of ea is ? 1 ? and the dsrpag<9> is also ? 1 ?. the lower 8 bits of dsrpag are concatenated to the wn<14:0> bits to form a 23-bit ea to access program memory. the dsrpag<8> decides which word should be addressed; when the bit is ? 0 ?, the lower word and when ? 1 ?, the upper word of the program memory is accessed. the entire program memory is divided into 512 eds pages, from 0x200 to 0x3ff, each consisting of 16k words of data. pages, 0x200 to 0x2ff, correspond to the lower words of the program memory, while 0x300 to 0x3ff correspond to the upper words of the program memory. using this eds technique, the entire program memory can be accessed. previously, the access to the upper word of the program memory was not supported. table 4-36 provides the corresponding 23-bit eds address for program memory with eds page and source addresses. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions will require one instruction cycle in addition to the specified execution time. all other instructions will require two instruction cycles in addition to the specified execution time. for operations that use psv, which are executed inside a repeat loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: ? execution in the first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction accessing data, using psv, to execute in a single cycle. table 4-36: eds program address with different pages and addresses dsrpag (data space read register) source address while indirect addressing 23-bit ea pointing to eds comment 0x200 0x8000 to 0xffff 0x000000 to 0x007ffe lower words of 4m program instructions (8 mbytes) for read operations only. ? ? ? ? ? ? 0x2ff 0x7f8000 to 0x7ffffe 0x300 0x000001 to 0x007fff upper words of 4m program instructions (4 mbytes remaining, 4 mbytes are phantom bytes) for read operations only. ? ? ? ? ? ? 0x3ff 0x7f8001 to 0x7fffff 0x000 invalid address address error trap (1) note 1: when the source/destination address is above 0x8000 and dsrpag/dswpag is ? 0 ?, an address error trap will occur.
pic24fj256gb210 family ds39975a-page 76 ? 2010 microchip technology inc. figure 4-10: program space visibility operation to access lower word figure 4-11: program space visibility operation to access higher word 23 15 0 dsrpag data space program space 0000h 8000h ffffh 202h 000000h 7ffffeh 010000h 017ffeh when dsrpag<9:8> = 10 and ea<15> = 1 eds window the data in the page designated by dsrpag is mapped into the upper half of the data memory space.... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the eds area. this corre- sponds exactly to the same lower 15 bits of the actual program space address. 23 15 0 dsrpag data space program space 0000h 8000h ffffh 302h 000000h 7ffffeh 010001h 017fffh when dsrpag<9:8> = 11 and ea<15> = 1 the data in the page designated by dsrpag is mapped into the upper half of the data memory space.... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the eds area. this corre- sponds exactly to the same lower 15 bits of the actual program space address. eds window
? 2010 microchip technology inc. ds39975a-page 77 pic24fj256gb210 family example 4-3: eds read code from program memory in assembly ; set the eds page from where the data to be read mov #0x0202 , w0 mov w0 , dsrpag ;page 0x202, consisting lower words, is selected for read mov #0x000a , w1 ;select the location (0x0a) to be read bset w1 , #15 ;set the msb of the base address, enable eds mode ;read a byte from the selected location mov.b [w1++] , w2 ;read low byte mov.b [w1++] , w3 ;read high byte ;read a word from the selected location mov [w1] , w2 ; ;read double - word from the selected location mov.d [w1] , w2 ;two word read, stored in w2 and w3
pic24fj256gb210 family ds39975a-page 78 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 79 pic24fj256gb210 family 5.0 flash program memory the pic24fj256gb210 family of devices contains internal flash program memory for storing and execut- ing application code. the program memory is readable, writable and erasable. the flash can be programmed in four ways: ? in-circuit serial programming? (icsp?) ? run-time self-programming (rtsp) ?jtag ? enhanced in-circuit serial programming (enhanced icsp) icsp allows a pic24fj256gb210 family device to be serially programmed while in the end application circuit. this is simply done with two lines for the programming clock and programming data (named pgecx and pgedx, respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may write program memory data in blocks of 64 instruc- tions (192 bytes) at a time and erase program memory in blocks of 512 instructions (1536 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using the tblpag<7:0> bits and the effective address (ea) from a w register, specified in the table instruction, as shown in figure 5-1. the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 4. ?program memory? (ds39715). the information in this data sheet supersedes the information in the frm. 0 program counter 24 bits program tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 0 1 / 0 select table instruction counter using user/configuration space select
pic24fj256gb210 family ds39975a-page 80 ? 2010 microchip technology inc. 5.2 rtsp operation the pic24f flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. it is also possible to program single words. the 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. when data is written to program memory using tblwt instructions, the data is not written directly to memory. instead, data written using table writes is stored in holding latches until the programming sequence is executed. any number of tblwt instructions can be executed and a write will be successfully performed. however, 64 tblwt instructions are required to write the full row of memory. to ensure that no data is corrupted during a write, any unused address should be programmed with ffffffh. this is because the holding latches reset to an unknown state, so if the addresses are left in the reset state, they may overwrite the locations on rows which were not rewritten. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. data can be loaded in any order and the holding regis- ters can be written to multiple times before performing a write operation. subsequent writes, however, will wipe out any previous writes. all of the table write operations are single-word writes (2 instruction cycles), because only the buffers are writ- ten. a programming cycle is required for programming each row. 5.3 jtag operation the pic24f family supports jtag boundary scan. boundary scan can improve the manufacturing process by verifying pin to pcb connectivity. 5.4 enhanced in-circuit serial programming enhanced in-circuit serial programming uses an on-board bootloader, known as the program executive, to manage the programming process. using an spi data frame format, the program executive can erase, program and verify program memory. for more information on enhanced icsp, see the device programming specification. 5.5 control registers there are two sfrs used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register (register 5-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. nvmkey is a write-only register that is used for write protection. to start a pr ogramming or erase sequence, the user must consecutively write 55h and aah to the nvmkey register. refer to section 5.6 ?programming operations? for further details. 5.6 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. during a programming or erase operation, the processor stalls (waits) until the operation is finished. setting the wr bit (nvmcon<15>) starts the opera- tion and the wr bit is automatically cleared when the operation is finished. note: writing to a location multiple times without erasing is not recommended.
? 2010 microchip technology inc. ds39975a-page 81 pic24fj256gb210 family register 5-1: nvmcon: flash memory control register r/s-0, hc (1) r/w-0 (1) r-0, hsc (1) u-0 u-0 u-0 u-0 u-0 wr wren wrerr ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 (1) u-0 u-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 (1) ?erase ? ?nvmop3 (2) nvmop2 (2) nvmop1 (2) nvmop0 (2) bit 7 bit 0 legend: s = settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hc = hardware clearable bit bit 15 wr: write control bit (1) 1 = initiates a flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit (1) 1 = enables flash program/erase operations 0 = inhibits flash program/erase operations bit 13 wrerr: write sequence error flag bit (1) 1 = an improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit (1) 1 = performs the erase operation specified by nvmop<3:0> on the next wr command 0 = performs the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation select bits (1,2) 1111 = memory bulk erase operation (erase = 1 ) or no operation (erase = 0 ) (3) 0011 = memory word program operation (erase = 0 ) or no operation (erase = 1 ) 0010 = memory page erase operation (erase = 1 ) or no operation (erase = 0 ) 0001 = memory row program operation (erase = 0 ) or no operation (erase = 1 ) note 1: these bits can only be reset on por. 2: all other combinations of nvmop<3:0> are unimplemented. 3: available in icsp? mode only; refer to the device programming specification.
pic24fj256gb210 family ds39975a-page 82 ? 2010 microchip technology inc. 5.6.1 programming algorithm for flash program memory the user can program one row of flash program memory at a time. to do this, it is necessary to erase the 8-row erase block containing the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 5-1): a) set the nvmop bits (nvmcon<3:0>) to ? 0010 ? to configure for block erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the block to be erased into the tblpag and w registers. c) write 55h to nvmkey. d) write aah to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the dura- tion of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 5-3). 5. write the program block to flash memory: a) set the nvmop bits to ? 0001 ? to configure for row programming. clear the erase bit and set the wren bit. b) write 55h to nvmkey. c) write aah to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash memory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incrementing the value in tblpag, until all 512 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 5-4. example 5-1: erasing a program memo ry block (assembly language code) ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize program memory (pm) page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea<15:0> pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov.b #0x55, w0 mov w0, nvmkey ; write the 0x55 key mov.b #0xaa, w1 ; mov w1, nvmkey ; write the 0xaa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
? 2010 microchip technology inc. ds39975a-page 83 pic24fj256gb210 family example 5-2: erasing a program memo ry block (?c? language code) example 5-3: loading the write buffers example 5-4: initiating a programming sequence // c example using mplab c30 unsigned long progaddr = 0xxxxxxx; // address of row to write unsigned int offset; //set up pointer to the first memory location to be written tblpag = progaddr>>16; // initialize pm page boundary sfr offset = progaddr & 0xffff; // initialize lower word of address __builtin_tblwtl(offset, 0x0000); // set base address of erase block // with dummy latch write nvmcon = 0x4042; // initialize nvmcon asm("disi #5"); // block all interrupts with priority <7 // for next 5 instructions __builtin_write_nvm(); // check function to perform unlock // sequence and set wr ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ? ? ? ; 63rd_program_word mov #low_word_63, w2 ; mov #high_byte_63, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov.b #0x55, w0 mov w0, nvmkey ; write the 0x55 key mov.b #0xaa, w1 ; mov w1, nvmkey ; write the 0xaa key bset nvmcon, #wr ; start the programming sequence nop ; required delays nop btsc nvmcon, #15 ; and wait for it to be bra $-2 ; completed
pic24fj256gb210 family ds39975a-page 84 ? 2010 microchip technology inc. 5.6.2 programming a single word of flash program memory if a flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. the tblpag register is loaded with the 8 most significant bytes (msb) of the flash address. the tblwtl and tblwth instructions write the desired data into the write latches and specify the lower 16 bits of the pro- gram memory address to write to. to configure the nvmcon register for a word write, set the nvmop bits (nvmcon<3:0>) to ? 0011 ?. the write is performed by executing the unlock sequence and setting the wr bit (see example 5-5). an equivalent procedure in ?c? compiler, using the mplab c30 compiler and built-in hardware functions, is shown in example 5-6. example 5-5: programming a single word of flash program memory example 5-6: programming a single word of flash program memory (?c? language code) ; setup a pointer to data program memory mov #tblpage(prog_addr), w0 ; mov w0, tblpag ;initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ;initialize a register with program memory address mov #low_word_n, w2 ; mov #high_byte_n, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; setup nvmcon for programming one word to data program memory mov #0x4003, w0 ; mov w0, nvmcon ; set nvmop bits to 0011 disi #5 ; disable interrupts while the key sequence is written mov.b #0x55, w0 ; write the key sequence mov w0, nvmkey mov.b #0xaa, w0 mov w0, nvmkey bset nvmcon, #wr ; start the write cycle nop ; required delays nop // c example using mplab c30 unsigned int offset; unsigned long progaddr = 0xxxxxxx; // address of word to program unsigned int progdatal = 0xxxxx; // data to program lower word unsigned char progdatah = 0xxx; // data to program upper byte //set up nvmcon for word programming nvmcon = 0x4003; // initialize nvmcon //set up pointer to the first memory location to be written tblpag = progaddr>>16; // initialize pm page boundary sfr offset = progaddr & 0xffff; // initialize lower word of address //perform tblwt instructions to write latches __builtin_tblwtl(offset, progdatal); // write to address low word __builtin_tblwth(offset, progdatah); // write to upper byte asm(?disi #5?); // block interrupts with priority <7 // for next 5 instructions __builtin_write_nvm(); // c30 function to perform unlock // sequence and set wr
? 2010 microchip technology inc. ds39975a-page 85 pic24fj256gb210 family 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ?mclr : pin reset ?swr: reset instruction ? wdt: watchdog timer reset ? bor: brown-out reset ? cm: configuration mismatch reset ? trapr: trap conflict reset ? iopuwr: illegal opcode reset ? uwr: uninitialized w register reset a simplified block diagram of the reset module is shown in figure 6-1. any active source of reset will make the sysrst signal active. many registers associated with the cpu and peripherals are forced to a known reset state. most registers are unaffected by a reset; their status is unknown on por and unchanged by all other resets. all types of device reset will set a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1). a por will clear all bits, except for the bor and por (rcon<1:0>) bits, which are set. the user may set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software will not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this data sheet. figure 6-1: reset sy stem block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 7. ?reset? (ds39712). the infor- mation in this data sheet supersedes the information in the frm. note: refer to the specific peripheral or cpu section of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. mclr v dd v dd rise detect por sleep or idle brown-out reset enable voltage regulator reset instruction wdt module glitch filter bor trap conflict illegal opcode uninitialized w register sysrst configuration mismatch
pic24fj256gb210 family ds39975a-page 86 ? 2010 microchip technology inc. register 6-1: rcon: re set control register (1) r/w-0, hs r/w-0, hs u-0 u-0 u-0 u-0 r/w-0, hs r/w-0 trapr iopuwr ? ? ? ?cmvregs (3) bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register is used as an address pointer and caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 cm: configuration word mismatch reset flag bit 1 = a configuration word mismatch reset has occurred 0 = a configuration word mismatch reset has not occurred bit 8 vregs: voltage regulator standby enable bit (3) 1 = program memory and regulator remain active during sleep/idle 0 = program memory power is removed and regulator goes to standby during seep/idle bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 =a reset instruction has been executed 0 =a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode note 1: all of the reset status bits may be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled , regardless of the swdten bit setting. 3: re-enabling the regulator after it enters standby mode will add a delay, t vreg , when waking up from sleep. applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.
? 2010 microchip technology inc. ds39975a-page 87 pic24fj256gb210 family table 6-1: reset flag bit operation bit 2 idle: wake-up from idle flag bit 1 = device has been in idle mode 0 = device has not been in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred note that bor is also set after a power-on reset. 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register (1) (continued) note 1: all of the reset status bits may be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled , regardless of the swdten bit setting. 3: re-enabling the regulator after it enters standby mode will add a delay, t vreg , when waking up from sleep. applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. flag bit setting event clearing event trapr (rcon<15>) trap conflict event por iopuwr (rcon<14>) illegal opcode or uninitialized w register access por cm (rcon<9>) configuration mismatch reset por extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por wdto (rcon<4>) wdt time-out clrwdt, pwrsav instruction, por sleep (rcon<3>) pwrsav #0 instruction por idle (rcon<2>) pwrsav #1 instruction por bor (rcon<1>) por, bor ? por (rcon<0>) por ? note: all reset flag bits may be set or cleared by the user software.
pic24fj256gb210 family ds39975a-page 88 ? 2010 microchip technology inc. 6.1 special function register reset states most of the special function registers (sfrs) associ- ated with the pic24f cpu and peripherals are reset to a particular value at a device reset. the sfrs are grouped by their peripheral or cpu function and their reset values are specified in each section of this manual. the reset value for each sfr does not depend on the type of reset, with the exception of four registers. the reset value for the reset control register, rcon, will depend on the type of device reset. the reset value for the oscillator control register, osccon, will depend on the type of reset and the programmed values of the fnosc bits in flash configuration word 2 (cw2) (see table 6-2). the rcfgcal and nvmcon registers are only affected by a por. 6.2 device reset times the reset times for various types of device reset are summarized in table 6-3. note that the system reset signal, sysrst , is released after the por delay time expires. the time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the oscillator start-up timer (ost) and the pll lock time. the ost and pll lock times occur in parallel with the applicable sysrst delay times. the fail-safe clock monitor (fscm) delay determines the time at which the fscm begins to monitor the system clock source after the sysrst signal is released. 6.3 clock source selection at reset if clock switching is enabled, the system clock source at device reset is chosen, as shown in table 6-2. if clock switching is disabled, the system clock source is always selected according to the oscillator configuration bits. refer to section 8.0 ?oscillator configuration? for further details. table 6-2: oscillator selection vs. type of reset (clock switching enabled) reset type clock source determinant por fnosc configuration bits (cw2<10:8>) bor mclr cosc control bits (osccon<14:12>) wdto swr
? 2010 microchip technology inc. ds39975a-page 89 pic24fj256gb210 family table 6-3: reset delay times for various device resets reset type clock source sysrst delay system clock delay notes por (7) ec t por + t startup + t rst ? 1, 2, 3 ecpll t por + t startup + t rst t lock 1, 2, 3, 5 xt, hs, sosc t por + t startup + t rst t ost 1, 2, 3, 4 xtpll, hspll t por + t startup + t rst t ost + t lock 1, 2, 3, 4, 5 frc, frcdiv t por + t startup + t rst t frc 1, 2, 3, 6, 7 frcpll t por + t startup + t rst t frc + t lock 1, 2, 3, 5, 6 lprc t por + t startup + t rst t lprc 1, 2, 3, 6 bor ec t startup + t rst ? 2, 3 ecpll t startup + t rst t lock 2, 3, 5 xt, hs, sosc t startup + t rst t ost 2, 3, 4 xtpll, hspll t startup + t rst t ost + t lock 2, 3, 4, 5 frc, frcdiv t startup + t rst t frc 2, 3, 6, 7 frcpll t startup + t rst t frc + t lock 2, 3, 5, 6 lprc t startup + t rst t lprc 2, 3, 6 mclr any clock t rst ? 3 wdt any clock t rst ? 3 software any clock t rst ? 3 illegal opcode any clock t rst ? 3 uninitialized w any clock t rst ? 3 trap conflict any clock t rst ? 3 note 1: t por = power-on reset delay (10 ? s nominal). 2: t startup = t vreg (10 ? s nominal when vregs = 1 and when vregs = 0; depends upon wutsel<1:0> bits setting). 3: t rst = internal state reset time (32 ? s nominal). 4: t ost = oscillator start-up timer. a 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: t lock = pll lock time. 6: t frc and t lprc = rc oscillator start-up times. 7: if two-speed start-up is enabled, regardless of the prim ary oscillator selected, the device starts with frc so the system clock delay is just t frc , and in such cases, frc start-up time is valid. it switches to the primary oscillator after its respective clock delay.
pic24fj256gb210 family ds39975a-page 90 ? 2010 microchip technology inc. 6.3.1 por and long oscillator start-up times the oscillator start-up circuitry and its associated delay timers are not linked to the device reset delays that occur at power-up. some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after sysrst is released: ? the oscillator circuit has not begun to oscillate. ? the oscillator start-up timer has not expired (if a crystal oscillator is used). ? the pll has not achieved a lock (if pll is used). the device will not begin to execute code until a valid clock source has been released to the system. there- fore, the oscillator and pll start-up delays must be considered when the reset delay time must be known. 6.3.2 fail-safe clock monitor (fscm) and device resets if the fscm is enabled, it will begin to monitor the system clock source when sysrst is released. if a valid clock source is not available at this time, the device will automatically switch to the frc oscillator and the user can switch to the desired crystal oscillator in the trap service routine (tsr).
? 2010 microchip technology inc. ds39975a-page 91 pic24fj256gb210 family 7.0 interrupt controller the pic24f interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the pic24f cpu. it has the following features: ? up to 8 processor exceptions and software traps ? seven user-selectable priority levels ? interrupt vector table (ivt) with up to 118 vectors ? unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 7.1 interrupt vector table the interrupt vector table (ivt) is shown in figure 7-1. the ivt resides in program memory, starting at location 000004h. the ivt contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. all other things being equal, lower addresses have a higher natural priority. for example, the interrupt asso- ciated with vector 0 will take priority over interrupts at any other vector address. pic24fj256gb210 family devices implement non-maskable traps and unique interrupts. these are summarized in table 7-1 and table 7-2. 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 7-1. the altivt (intcon2<15>) control bit provides access to the aivt. if the altivt bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the inter- rupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 7.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the pic24f devices clear their registers in response to a reset, which forces the pc to zero. the micro- controller then begins program execution at location, 000000h. the user programs a goto instruction at the reset address, which redirects program execution to the appropriate start-up routine. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 8. ?interrupts? (ds39707). the information in this data sheet supersedes the information in the frm. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction.
pic24fj256gb210 family ds39975a-page 92 ? 2010 microchip technology inc. figure 7-1: pic24f interrupt vector table table 7-1: trap vector details note 1: see table 7-2 for the interrupt vector list. reset ? goto instruction 000000h reset ? goto address 000002h reserved 000004h oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000014h interrupt vector 1 ? ? ? interrupt vector 52 00007ch interrupt vector 53 00007eh interrupt vector 54 000080h ? ? ? interrupt vector 116 0000fch interrupt vector 117 0000feh reserved 000100h reserved 000102h reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000114h interrupt vector 1 ? ? ? interrupt vector 52 00017ch interrupt vector 53 00017eh interrupt vector 54 000180h ? ? ? interrupt vector 116 interrupt vector 117 0001feh start of code 000200h decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) vector number ivt address aivt address trap source 0 000004h 000104h reserved 1 000006h 000106h oscillator failure 2 000008h 000108h address error 3 00000ah 00010ah stack error 4 00000ch 00010ch math error 5 00000eh 00010eh reserved 6 000010h 000110h reserved 7 000012h 000112h reserved
? 2010 microchip technology inc. ds39975a-page 93 pic24fj256gb210 family table 7-2: implemented interrupt vectors interrupt source vector number ivt address aivt address interrupt bit locations flag enable priority adc1 conversion done 13 00002eh 00012eh ifs0<13> iec0<13> ipc3<6:4> comparator event 18 000038h 000138h ifs1<2> iec1<2> ipc4<10:8> crc generator 67 00009ah 00019ah ifs4<3> iec4<3> ipc16<14:12> ctmu event 77 0000aeh 0001aeh ifs4<13> iec4<13> ipc19<6:4> external interrupt 0 0 000014h 000114h ifs0<0> iec0<0> ipc0<2:0> external interrupt 1 20 00003ch 00013ch ifs1<4> iec1<4> ipc5<2:0> external interrupt 2 29 00004eh 00014eh ifs1<13> iec1<13> ipc7<6:4> external interrupt 3 53 00007eh 00017eh ifs3<5> iec3<5> ipc13<6:4> external interrupt 4 54 000080h 000180h ifs3<6> iec3<6> ipc13<10:8> i2c1 master event 17 000036h 000136h ifs1<1> iec1<1> ipc4<6:4> i2c1 slave event 16 000034h 000134h ifs1<0> iec1<0> ipc4<2:0> i2c2 master event 50 000078h 000178h ifs3<2> iec3<2> ipc12<10:8> i2c2 slave event 49 000076h 000176h ifs3<1> iec3<1> ipc12<6:4> i2c3 master event 85 0000beh 0001beh ifs5<5> iec5<5> ipc21<6:4> i2c3 slave event 84 0000bch 0001bch ifs5<4> iec5<4> ipc21<2:0> input capture 1 1 000016h 000116h ifs0<1> iec0<1> ipc0<6:4> input capture 2 5 00001eh 00011eh ifs0<5> iec0<5> ipc1<6:4> input capture 3 37 00005eh 00015eh ifs2<5> iec2<5> ipc9<6:4> input capture 4 38 000060h 000160h ifs2<6> iec2<6> ipc9<10:8> input capture 5 39 000062h 000162h ifs2<7> iec2<7> ipc9<14:12> input capture 6 40 000064h 000164h ifs2<8> iec2<8> ipc10<2:0> input capture 7 22 000040h 000140h ifs1<6> iec1<6> ipc5<10:8> input capture 8 23 000042h 000142h ifs1<7> iec1<7> ipc5<14:12> input capture 9 93 0000ceh 0001ceh ifs5<13> iec5<13> ipc23<6:4> input change notification (icn) 19 00003ah 00013ah ifs1<3> iec1<3> ipc4<14:12> low-voltage detect (lvd) 72 0000a4h 0001a4h ifs4<8> iec4<8> ipc18<2:0> output compare 1 2 000018h 000118h ifs0<2> iec0<2> ipc0<10:8> output compare 2 6 000020h 000120h ifs0<6> iec0<6> ipc1<10:8> output compare 3 25 000046h 000146h ifs1<9> iec1<9> ipc6<6:4> output compare 4 26 000048h 000148h ifs1<10> iec1<10> ipc6<10:8> output compare 5 41 000066h 000166h ifs2<9> iec2<9> ipc10<6:4> output compare 6 42 000068h 000168h ifs2<10> iec2<10> ipc10<10:8> output compare 7 43 00006ah 00016ah ifs2<11> iec2<11> ipc10<14:12> output compare 8 44 00006ch 00016ch ifs2<12> iec2<12> ipc11<2:0> output compare 9 92 0000cch 0001cch ifs5<12> iec5<12> ipc23<2:0> enhanced parallel master port (epmp) 45 00006eh 00016eh ifs2<13> iec2<13> ipc11<6:4> real-time clock and calendar (rtcc) 62 000090h 000190h ifs3<14> iec3<14> ipc15<10:8> spi1 error 9 000026h 000126h ifs0<9> iec0<9> ipc2<6:4> spi1 event 10 000028h 000128h ifs0<10> iec0<10> ipc2<10:8> spi2 error 32 000054h 000154h ifs2<0> iec2<0> ipc8<2:0> spi2 event 33 000056h 000156h ifs2<1> iec2<1> ipc8<6:4> spi3 error 90 0000c8h 0001c8h ifs5<10> iec5<10> ipc22<10:8> spi3 event 91 0000cah 0001cah ifs5<11> iec5<11> ipc22<14:12>
pic24fj256gb210 family ds39975a-page 94 ? 2010 microchip technology inc. 7.3 interrupt control and status registers the pic24fj256gb210 family of devices implements a total of 37 registers for the interrupt controller: ? intcon1 ? intcon2 ? ifs0 through ifs5 ? iec0 through iec5 ? ipc0 through ipc23 (except ipc14 and ipc17) ?inttreg global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the inter- rupt nesting disable (nstdis) bit, as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate interrupt vector table (aivt). the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or an external signal and is cleared via software. the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. the ipcx registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into the vector number (vecnum<6:0>) and the interrupt priority level (ilr<3:0>) bit fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the order of their vector numbers, as shown in table 7-2. for example, the int0 (external interrupt 0) is shown as having a vector number and a natural order priority of 0. thus, the int0if status bit is found in ifs0<0>, the int0ie enable bit in iec0<0> and the int0ip<2:0> priority bits in the first position of ipc0 (ipc0<2:0>). although they are not specifically part of the interrupt control hardware, two of the cpu control registers con- tain bits that control interrupt functionality. the alu status register (sr) contains the ipl<2:0> bits (sr<7:5>). these indicate the current cpu interrupt priority level. the user can change the current cpu priority level by writing to the ipl bits. timer1 3 00001ah 00011ah ifs0<3> iec0<3> ipc0<14:12> timer2 7 000022h 000122h ifs0<7> iec0<7> ipc1<14:12> timer3 8 000024h 000124h ifs0<8> iec0<8> ipc2<2:0> timer4 27 00004ah 00014ah ifs1<11> iec1<11> ipc6<14:12> timer5 28 00004ch 00014ch ifs1<12> iec1<12> ipc7<2:0> uart1 error 65 000096h 000196h ifs4<1> iec4<1> ipc16<6:4> uart1 receiver 11 00002ah 00012ah ifs0<11> iec0<11> ipc2<14:12> uart1 transmitter 12 00002ch 00012ch ifs0<12> iec0<12> ipc3<2:0> uart2 error 66 000098h 000198h ifs4<2> iec4<2> ipc16<10:8> uart2 receiver 30 000050h 000150h ifs1<14> iec1<14> ipc7<10:8> uart2 transmitter 31 000052h 000152h ifs1<15> iec1<15> ipc7<14:12> uart3 error 81 0000b6h 0001b6h ifs5<1> iec5<1> ipc20<6:4> uart3 receiver 82 0000b8h 0001b8h ifs5<2> iec5<2> ipc20<10:8> uart3 transmitter 83 0000bah 0001bah ifs5<3> iec5<3> ipc20<14:12> uart4 error 87 0000c2h 0001c2h ifs5<7> iec5<7> ipc21<14:12> uart4 receiver 88 0000c4h 0001c4h ifs5<8> iec5<8> ipc22<2:0> uart4 transmitter 89 0000c6h 0001c6h ifs5<9> iec5<9> ipc22<6:4> usb interrupt 86 0000c0h 0001c0h ifs5<6> iec5<6> ipc21<10:8> table 7-2: implemented interrupt vectors (continued) interrupt source vector number ivt address aivt address interrupt bit locations flag enable priority
? 2010 microchip technology inc. ds39975a-page 95 pic24fj256gb210 family the corcon register contains the ipl3 bit, which, together with ipl<2:0>, indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. the interrupt controller has the interrupt controller test register, inttreg, which displays the status of the interrupt controller. when an interrupt request occurs, it?s associated vector number and the new interrupt pri- ority level are latched into inttreg. this information can be used to determine a specific interrupt source if a generic isr is used for multiple vectors (such as when isr remapping is used in bootloader applica- tions) or to check if another interrupt is pending while in an isr. all interrupt registers are described in register 7-1 through register 7-38 in the succeeding pages. register 7-1: sr: alu status register (in cpu) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0, hsc ? ? ? ? ? ? ? dc (1) bit 15 bit 8 r/w-0, hsc r/w-0, hsc r/w-0, hsc r-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc ipl2 (2,3) ipl1 (2,3) ipl0 (2,3) ra (1) n (1) ov (1) z (1) c (1) bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2,3) 111 = cpu interrupt priority level is 7 (15); user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: see register 3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to interrupt control functions. 2: the ipl bits are concatenated with the ipl3 (corcon<3>) bit to form the cpu interrupt priority level. the value in parentheses indicates the interrupt priority level if ipl3 = 1 . 3: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 .
pic24fj256gb210 family ds39975a-page 96 ? 2010 microchip technology inc. register 7-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0, hsc r-1 u-0 u-0 ? ? ? ?ipl3 (1) r ? ? bit 7 bit 0 legend: r = reserved bit c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit (1) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 reserved: read as ? 1 ? bit 1-0 unimplemented: read as ? 0 ? note 1: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level; see register 3-2 for bit description.
? 2010 microchip technology inc. ds39975a-page 97 pic24fj256gb210 family register 7-3: intcon1: in terrupt control register 1 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 nstdis ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs u-0 ? ? ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14-5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error trap status bit 1 = overflow trap has occurred 0 = overflow trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 98 ? 2010 microchip technology inc. register 7-4: intcon2: in terrupt control register 2 r/w-0 r-0, hsc u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate interrupt vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-5 unimplemented: read as ? 0 ? bit 4 int4ep: external interrupt 4 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 3 int3ep: external interrupt 3 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge
? 2010 microchip technology inc. ds39975a-page 99 pic24fj256gb210 family register 7-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs ? ? ad1if u1txif u1rxif spi1if spf1if t3if bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1if: a/d conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spf1if: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fj256gb210 family ds39975a-page 100 ? 2010 microchip technology inc. bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-5: ifs0: interrupt fla g status register 0 (continued) register 7-6: ifs1: interrupt flag status register 1 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs u-0 u2txif u2rxif int2if t5if t4if oc4if oc3if ? bit 15 bit 8 r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs ic8if ic7if ? int1if cnif cmif mi2c1if si2c1if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txif: uart2 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 u2rxif: uart2 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 t5if: timer5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4if: timer4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 oc4if: output compare channel 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 oc3if: output compare channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 unimplemented: read as ? 0 ? bit 7 ic8if: input capture channel 8 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic7if: input capture channel 7 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2010 microchip technology inc. ds39975a-page 101 pic24fj256gb210 family bit 5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 cmif: comparator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 mi2c1if: master i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: slave i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-6: ifs1: interrupt fla g status register 1 (continued) register 7-7: ifs2: interrupt flag status register 2 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs ? ? pmpif oc8if oc7if oc6if oc5if ic6if bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs u-0 u-0 u-0 r/w-0, hs r/w-0, hs ic5if ic4if ic3if ? ? ? spi2if spf2if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 pmpif: parallel master port interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 oc8if: output compare channel 8 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 oc7if: output compare channel 7 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 oc6if: output compare channel 6 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 oc5if: output compare channel 5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fj256gb210 family ds39975a-page 102 ? 2010 microchip technology inc. bit 8 ic6if: input capture channel 6 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 ic5if: input capture channel 5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic4if: input capture channel 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic3if: input capture channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2if: spi2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 spf2if: spi2 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-7: ifs2: interrupt fla g status register 2 (continued)
? 2010 microchip technology inc. ds39975a-page 103 pic24fj256gb210 family register 7-8: ifs3: interrupt flag status register 3 u-0 r/w-0, hs u-0 u-0 u-0 u-0 u-0 u-0 ?rtcif ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0, hs r/w-0, hs u-0 u-0 r/w-0, hs r/w-0, hs u-0 ? int4if int3if ? ?mi2c2ifsi2c2if ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcif: real-time clock/calendar interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-7 unimplemented: read as ? 0 ? bit 6 int4if: external interrupt 4 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 int3if: external interrupt 3 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4-3 unimplemented: read as ? 0 ? bit 2 mi2c2if: master i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 si2c2if: slave i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 104 ? 2010 microchip technology inc. register 7-9: ifs4: interrupt flag status register 4 u-0 u-0 r/w-0, hs u-0 u-0 u-0 u-0 r/w-0, hs ? ?ctmuif ? ? ? ?lvdif bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs u-0 ? ? ? ? crcif u2erif u1erif ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuif: ctmu interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-9 unimplemented: read as ? 0 ? bit 8 lvdif: low-voltage detect interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7-4 unimplemented: read as ? 0 ? bit 3 crcif: crc generator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 u2erif: uart2 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 u1erif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 105 pic24fj256gb210 family register 7-10: ifs5: interrupt flag status register 5 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs ? ? ic9if oc9if spi3if spf3if u4txif u4rxif bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs u-0 u4erif usb1if mi2c3if si2c3if u3txif u3rxif u3erif ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ic9if: input capture channel 9 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 oc9if: output compare channel 9 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 spi3if: spi3 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spf3if: spi3 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 u4txif: uart4 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 u4rxif: uart4 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 u4erif: uart4 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 usb1if: usb1 (usb otg) interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 mi2c3if: master i2c3 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 si2c3if: slave i2c3 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 u3txif: uart3 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 u3rxif: uart3 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fj256gb210 family ds39975a-page 106 ? 2010 microchip technology inc. bit 1 u3erif: uart3 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ? register 7-10: ifs5: interrupt fla g status register 5 (continued) register 7-11: iec0: interrupt enable control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1ie: a/d conversion complete interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 spi1ie: spi1 transfer complete interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 9 spf1ie: spi1 fault interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 107 pic24fj256gb210 family bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled register 7-11: iec0: interrupt enable control register 0 (continued) register 7-12: iec1: interrupt enable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u2txie u2rxie int2ie (1) t5ie t4ie oc4ie oc3ie ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic8ie ic7ie ?int1ie (1) cnie cmie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txie: uart2 transmitter interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 u2rxie: uart2 receiver interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13 int2ie: external interrupt 2 enable bit (1) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 t5ie: timer5 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 t4ie: timer4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 oc4ie: output compare channel 4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled note 1: if an external interrupt is enabled, the interrupt input must also be configured to an available rpx or rpix pin. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 108 ? 2010 microchip technology inc. bit 9 oc3ie: output compare channel 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 unimplemented: read as ? 0 ? bit 7 ic8ie: input capture channel 8 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6 ic7ie: input capture channel 7 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit (1) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 cmie: comparator interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 mi2c1ie: master i2c1 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 si2c1ie: slave i2c1 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled register 7-12: iec1: interrupt enable control register 1 (continued) note 1: if an external interrupt is enabled, the interrupt input must also be configured to an available rpx or rpix pin. see section 10.4 ?peripheral pin select (pps)? for more information.
? 2010 microchip technology inc. ds39975a-page 109 pic24fj256gb210 family register 7-13: iec2: interrupt enable control register 2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? pmpie oc8ie oc7ie oc6ie oc5ie ic6ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 ic5ie ic4ie ic3ie ? ? ? spi2ie spf2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 pmpie: parallel master port interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 oc8ie: output compare channel 8 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 oc7ie: output compare channel 7 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 oc6ie: output compare channel 6 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 9 oc5ie: output compare channel 5 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 ic6ie: input capture channel 6 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7 ic5ie: input capture channel 5 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6 ic4ie: input capture channel 4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 ic3ie: input capture channel 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2ie: spi2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 spf2ie: spi2 fault interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
pic24fj256gb210 family ds39975a-page 110 ? 2010 microchip technology inc. register 7-14: iec3: interrupt enable control register 3 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ?rtcie ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 ?int4ie (1) int3ie (1) ? ?mi2c2iesi2c2ie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcie: real-time clock/calendar interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13-7 unimplemented: read as ? 0 ? bit 6 int4ie: external interrupt 4 enable bit (1) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 int3ie: external interrupt 3 enable bit (1) 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4-3 unimplemented: read as ? 0 ? bit 2 mi2c2ie: master i2c2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 si2c2ie: slave i2c2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 unimplemented: read as ? 0 ? note 1: if an external interrupt is enabled, the interrupt input must also be configured to an available rpx or rpix pin. see section 10.4 ?peripheral pin select (pps)? for more information.
? 2010 microchip technology inc. ds39975a-page 111 pic24fj256gb210 family register 7-15: iec4: interrupt enable control register 4 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 ? ?ctmuie ? ? ? ?lvdie bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 ? ? ? ? crcie u2erie u1erie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuie: ctmu interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12-9 unimplemented: read as ? 0 ? bit 8 lvdie: low-voltage detect interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7-4 unimplemented: read as ? 0 ? bit 3 crcie: crc generator interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 u2erie: uart2 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 u1erie: uart1 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 112 ? 2010 microchip technology inc. register 7-16: iec5: interrupt enable control register 5 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ic9ie oc9ie spi3ie spf3ie u4txie u4rxie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u4erie usb1ie mi2c3ie si2c3ie u3txie u3rxie u3erie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ic9ie: input capture channel 9 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 oc9ie: output compare channel 9 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 spi3ie: spi3 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spf3ie: spi3 fault interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 u4txie: uart4 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 u4rxie: uart4 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 u4erie: uart4 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 usb1ie: usb1 (usb otg) interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 mi2c3ie: master i2c3 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 si2c3ie: slave i2c3 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 u3txie: uart3 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 u3rxie: uart3 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled
? 2010 microchip technology inc. ds39975a-page 113 pic24fj256gb210 family bit 1 u3erie: uart3 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 unimplemented: read as ? 0 ? register 7-16: iec5: interrupt enable control register 5 (continued) register 7-17: ipc0: interrupt pr iority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 114 ? 2010 microchip technology inc. register 7-18: ipc1: interrupt pr iority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 115 pic24fj256gb210 family register 7-19: ipc2: interrupt pr iority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spf1ip2 spf1ip1 spf1ip0 ? t3ip2 t3ip1 t3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spf1ip<2:0>: spi1 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 116 ? 2010 microchip technology inc. register 7-20: ipc3: interrupt pr iority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip<2:0>: a/d conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2010 microchip technology inc. ds39975a-page 117 pic24fj256gb210 family register 7-21: ipc4: interrupt pr iority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? cnip2 cnip1 cnip0 ?cmip2cmip1cmip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c1ip2 mi2c1ip1 mi2c1ip0 ? si2c1ip2 si2c1ip1 si2c1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip<2:0>: input change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 cmip<2:0>: comparator interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 mi2c1ip<2:0>: master i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1ip<2:0>: slave i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 118 ? 2010 microchip technology inc. register 7-22: ipc5: interrupt pr iority control register 5 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic8ip2 ic8ip1 ic8ip0 ? ic7ip2 ic7ip1 ic7ip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int1ip2 int1ip1 int1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 ic8ip<2:0>: input capture channel 8 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 ic7ip<2:0>: input capture channel 7 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-3 unimplemented: read as ? 0 ? bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2010 microchip technology inc. ds39975a-page 119 pic24fj256gb210 family register 7-23: ipc6: interrupt pr iority control register 6 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t4ip2 t4ip1 t4ip0 ? oc4ip2 oc4ip1 oc4ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t4ip<2:0>: timer4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc4ip<2:0>: output compare channel 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 oc3ip<2:0>: output compare channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 120 ? 2010 microchip technology inc. register 7-24: ipc7: interrupt pr iority control register 7 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? int2ip2 int2ip1 int2ip0 ? t5ip2 t5ip1 t5ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u2txip<2:0>: uart2 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2rxip<2:0>: uart2 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t5ip<2:0>: timer5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2010 microchip technology inc. ds39975a-page 121 pic24fj256gb210 family register 7-25: ipc8: interrupt pr iority control register 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 spi2ip<2:0>: spi2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 spf2ip<2:0>: spi2 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 122 ? 2010 microchip technology inc. register 7-26: ipc9: interrupt pr iority control register 9 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic5ip2 ic5ip1 ic5ip0 ? ic4ip2 ic4ip1 ic4ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 ic5ip<2:0>: input capture channel 5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 ic4ip<2:0>: input capture channel 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic3ip<2:0>: input capture channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 123 pic24fj256gb210 family register 7-27: ipc10: interrupt priority control register 10 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? oc7ip2oc7ip1oc7ip0 ? oc6ip2 oc6ip1 oc6ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? oc5ip2 oc5ip1 oc5ip0 ? ic6ip2 ic6ip1 ic6ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 oc7ip<2:0>: output compare channel 7 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc6ip<2:0>: output compare channel 6 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 oc5ip<2:0>: output compare channel 5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 ic6ip<2:0>: input capture channel 6 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 124 ? 2010 microchip technology inc. register 7-28: ipc11: interrupt priority control register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? pmpip2 pmpip1 pmpip0 ? oc8ip2 oc8ip1 oc8ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 pmpip<2:0>: parallel master port interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 oc8ip<2:0>: output compare channel 8 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2010 microchip technology inc. ds39975a-page 125 pic24fj256gb210 family register 7-29: ipc12: interrupt priority control register 12 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? mi2c2ip2 mi2c2ip1 mi2c2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? si2c2ip2 si2c2ip1 si2c2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 mi2c2ip<2:0>: master i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 si2c2ip<2:0>: slave i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 126 ? 2010 microchip technology inc. register 7-30: ipc13: interrupt priority control register 13 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int4ip2 int4ip1 int4ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? int3ip2 int3ip1 int3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 int4ip<2:0>: external interrupt 4 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 int3ip<2:0>: external interrupt 3 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 127 pic24fj256gb210 family register 7-31: ipc15: interrupt priority control register 15 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? rtcip2 rtcip1 rtcip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 rtcip<2:0>: real-time clock and calendar interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 128 ? 2010 microchip technology inc. register 7-32: ipc16: interrupt priority control register 16 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 crcip<2:0>: crc generator error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2erip<2:0>: uart2 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 u1erip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 129 pic24fj256gb210 family register 7-33: ipc18: interrupt priority control register 18 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? lvdip2 lvdip1 lvdip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 lvdip<2:0>: low-voltage detect interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled register 7-34: ipc19: interrupt priority control register 19 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ctmuip<2:0>: ctmu interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 130 ? 2010 microchip technology inc. register 7-35: ipc20: interrupt priority control register 20 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u3txip2 u3txip1 u3txip0 ? u3rxip2 u3rxip1 u3rxip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? u3erip2 u3erip1 u3erip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u3txip<2:0>: uart3 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u3rxip<2:0>: uart3 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 u3erip<2:0>: uart3 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 131 pic24fj256gb210 family register 7-36: ipc21: interrupt priority control register 21 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u4erip2 u4erip1 u4erip0 ? usb1ip2 usb1ip1 usb1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c3ip2 mi2c3ip1 mi2c3ip0 ? si2c3ip2 si2c3ip1 si2c3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u4erip<2:0>: uart4 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 usb1ip<2:0>: usb1 (usb otg) interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 mi2c3ip<2:0>: master i2c3 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c3ip<2:0>: slave i2c3 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 132 ? 2010 microchip technology inc. register 7-37: ipc22: interrupt priority control register 22 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi3ip2 spi3ip1 spi3ip0 ? spf3ip2 spf3ip1 spf3ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u4txip2 u4txip1 u4txip0 ? u4rxip2 u4rxip1 u4rxip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 spi3ip<2:0>: spi3 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spf3ip<2:0>: spi3 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 u4txip<2:0>: uart4 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u4rxip<2:0>: uart4 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2010 microchip technology inc. ds39975a-page 133 pic24fj256gb210 family register 7-38: ipc23: interrupt priority control register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic9ip2 ic9ip1 ic9ip0 ? oc9ip2 oc9ip1 oc9ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ic9ip<2:0>: input capture channel 9 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 oc9ip<2:0>: output compare channel 9 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fj256gb210 family ds39975a-page 134 ? 2010 microchip technology inc. register 7-39: inttreg: interrupt controller test register r-0, hsc u-0 r/w-0 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc cpuirq ?vhold ? ilr3ilr2ilr1ilr0 bit 15 bit 8 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cpuirq: interrupt request from interrupt controller cpu bit 1 = an interrupt request has occurred but has not yet been acknowledged by the cpu; this happens when the cpu priority is higher than the interrupt priority 0 = no interrupt request is unacknowledged bit 14 unimplemented: read as ? 0 ? bit 13 vhold: vector number capture configuration bit 1 = the vecnum bits contain the value of the highest priority pending interrupt 0 = the vecnum bits contain the value of the last acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the cpu, even if other interrupts are pending) bit 12 unimplemented: read as ? 0 ? bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 ? ? ? 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 vecnum<5:0>: vector number of pending interrupt or last acknowledged interrupt bits vhold = 1 : the vecnum bits indicate the vector number (from 0 to 118) of the last interrupt to occur vhold = 0 : the vecnum bits indicate the vector number (from 0 to 118) of the interrupt request currently being handled
? 2010 microchip technology inc. ds39975a-page 135 pic24fj256gb210 family 7.4 interrupt setup procedures 7.4.1 initialization to configure an interrupt source: 1. set the nstdis (intcon1<15>) control bit if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate iecx register. 7.4.2 interrupt service routine (isr) the method that is used to declare an interrupt service routine (isr) and initialize the ivt with the correct vec- tor address will depend on the programming language (i.e., ?c? or assembler) and the language development toolsuite that is used to develop the application. in general, the user must clear the interrupt flag in the appropriate ifsx register for the source of the interrupt that the isr handles. otherwise, the isr will be re-entered immediately after exiting the routine. if the isr is coded in assembly language, it must be termi- nated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 7.4.3 trap service routine (tsr) a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 7.4.4 interrupt disable all user interrupts can be disabled using the following procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value 0eh with srl. to enable user interrupts, the pop instruction may be used to restore the previous sr value. note that only user interrupts with a priority level of 7 or less can be disabled. trap sources (levels 8-15) cannot be disabled. the disi instruction provides a convenient way to disable interrupts of priority levels, 1-6, for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized, such that all user interrupt sources are assigned to priority level 4.
pic24fj256gb210 family ds39975a-page 136 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 137 pic24fj256gb210 family 8.0 oscillator configuration the oscillator system for pic24fj256gb210 family devices has the following features: ? a total of four external and internal oscillator options as clock sources, providing 11 different clock modes ? an on-chip pll block to boost internal operating frequency on select internal and external oscillator sources, and to provide a precise clock source for peripherals, such as usb ? software controllable switching between various clock sources ? software controllable postscaler for selective clocking of cpu for system power savings ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown ? a separate and independently configurable system clock output for synchroni zing external hardware a simplified diagram of the oscillator system is shown in figure 8-1. figure 8-1: pic24fj256gb2 10 family clock diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 6. ?oscillator? (ds39700). the information in this data sheet supersedes the information in the frm. secondary oscillator soscen enable oscillator sosco sosci clock source option for other modules osci osco primary oscillator xt, hs, ec cpu peripherals postscaler clkdiv<10:8> wdt, pwrt 8 mhz frcdiv 31 khz (nominal) frc oscillator lprc oscillator sosc lprc postscaler clock control logic fail-safe clock monitor clkdiv<14:12> frc clko (nominal) xtpll, hspll ecpll,frcpll 8 mhz 4 mhz pll div plldiv<2:0> cpdiv<1:0> 48 mhz usb clock usb pll reference clock generator refo refocon<15:8> & pic24fj256gb210 family
pic24fj256gb210 family ds39975a-page 138 ? 2010 microchip technology inc. 8.1 cpu clocking scheme the system clock source can be provided by one of four sources: ? primary oscillator (posc) on the osci and osco pins ? secondary oscillator (sosc) on the sosci and sosco pins ? fast internal rc (frc) oscillator ? low-power internal rc (lprc) oscillator the primary oscillator and frc sources have the option of using the internal 24x pll block, which generates the usb module clock, and a separate system clock through the 96 mhz pll. refer to section 8.5 ?96 mhz pll block? for additional information. the internal frc provides an 8 mhz clock source. it can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. the selected clock source generates the processor and peripheral clock sources. the processor clock source is divided by two to produce the internal instruc- tion cycle clock, f cy . in this document, the instruction cycle clock is also denoted by f osc /2. the internal instruction cycle clock, f osc /2, can be provided on the osco i/o pin for some operating modes of the primary oscillator. 8.2 initial configuration on por the oscillator source (and operating mode) that is used at a device power-on reset (por) event is selected using configuration bit settings. the oscillator configu- ration bit settings are located in the configuration registers in the program memory (refer to section 26.1 ?configuration bits? for further details). the primary oscillator configuration bits, poscmd<1:0> (configu- ration word 2<1:0>) and the initial oscillator select configuration bits, fnosc<2:0> (configuration word 2<10:8>), select the oscillator source that is used at a por. the frc primary oscillator with postscaler (frcdiv) is the default (unprogrammed) selection. the secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. the configuration bits allow users to choose between the various clock modes, shown in table 8-1. 8.2.1 clock switching mode configuration bits the fcksm configuration bits (configuration word 2<7:6>) are used to jointly configure device clock switching and the fail-safe clock monitor (fscm). clock switching is enabled only when fcksm1 is programmed (? 0 ?). the fscm is enabled only when fcksm<1:0> are both programmed (? 00 ?). table 8-1: configuration bit va lues for clock selection oscillator mode oscillator source poscmd<1:0> fnosc<2:0> notes fast rc oscillator with postscaler (frcdiv) internal 11 111 1, 2 frc oscillator/16 (500 khz) internal 11 110 1 low-power rc oscillator (lprc) internal 11 101 1 secondary (timer1) oscillator (sosc) secondary 11 100 1 primary oscillator (xt) with pll module (xtpll) primary 01 011 ? primary oscillator (ec) with pll module (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 ? primary oscillator (xt) primary 01 010 ? primary oscillator (ec) primary 00 010 1 fast rc oscillator with pll module (frcpll) internal 11 001 1 fast rc oscillator (frc) internal 11 000 1 note 1: osco pin function is determined by the osciofcn configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device.
? 2010 microchip technology inc. ds39975a-page 139 pic24fj256gb210 family 8.3 control registers the following four special function registers control the operation of the oscillator: ? osccon ?clkdiv ?osctun ? refocon the osccon register (register 8-1) is the main con- trol register for the oscillator. it controls clock source switching and allows the monitoring of clock sources. the clkdiv register (register 8-2) controls the features associated with doze mode, as well as the postscaler for the frc oscillator. the osctun register (register 8-3) allows the user to fine tune the frc oscillator over a range of approximately 1.5%. the refocon register (register 8-5) controls the frequency of the reference clock out. register 8-1: osccon: os cillator control register u-0 r-x, hsc (1) r-x, hsc (1) r-x, hsc (1) u-0 r/w-x (1) r/w-x (1) r/w-x (1) ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 bit 15 bit 8 r/s-0 r/w-0 r-0, hsc (3) u-0 r/c-0, hs r/w-0 r/w-0 r/w-0 clklock iolock (2) lock ? cf poscen soscen oswen bit 7 bit 0 legend: c = clearable bit s = settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hs = hardware settable bit bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits (1) 111 = fast rc oscillator with postscaler (frcdiv) 110 = fast rc/16 oscillator 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits (1) 111 = fast rc oscillator with postscaler (frcdiv) 110 = fast rc/16 oscillator 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) note 1: reset values for these bits are determined by the fnosc configuration bits. 2: the state of the iolock bit can only be changed once an unlocking sequence has been executed. in addition, if the iol1way configuration bit is ? 1 ?, once the iolock bit is set, it cannot be cleared. 3: also resets to ? 0 ? during any valid clock switch or whenever a non pll clock mode is selected.
pic24fj256gb210 family ds39975a-page 140 ? 2010 microchip technology inc. bit 7 clklock: clock selection lock enabled bit if fscm is enabled (fcksm1 = 1 ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified by setting the oswen bit if fscm is disabled (fcksm1 = 0 ): clock and pll selections are never locked and may be modified by setting the oswen bit. bit 6 iolock: i/o lock enable bit (2) 1 = i/o lock is active 0 = i/o lock is not active bit 5 lock: pll lock status bit (3) 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 unimplemented: read as ? 0 ? bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected bit 2 poscen: primary oscillator sleep enable bit 1 = primary oscillator continues to operate during sleep mode 0 = primary oscillator is disabled during sleep mode bit 1 soscen: 32 khz secondary oscillator (sosc) enable bit 1 = enable the secondary oscillator 0 = disable the secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to the clock source specified by the nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: oscillato r control register (continued) note 1: reset values for these bits are determined by the fnosc configuration bits. 2: the state of the iolock bit can only be changed once an unlocking sequence has been executed. in addition, if the iol1way configuration bit is ? 1 ?, once the iolock bit is set, it cannot be cleared. 3: also resets to ? 0 ? during any valid clock switch or whenever a non pll clock mode is selected.
? 2010 microchip technology inc. ds39975a-page 141 pic24fj256gb210 family register 8-2: clkdiv: clock divider register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 roi doze2 doze1 doze0 dozen (1) rcdiv2 rcdiv1 rcdiv0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0 u-0 u-0 u-0 u-0 cpdiv1 cpdiv0 pllen reserved ? ? ? ? bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts clear the dozen bit and reset the cpu peripheral clock ratio to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: cpu peripheral clock ratio select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 dozen: doze enable bit (1) 1 = doze<2:0> bits specify the cpu peripheral clock ratio 0 = cpu peripheral clock ratio is set to 1:1 bit 10-8 rcdiv<2:0>: frc postscaler select bits 111 = 31.25 khz (divide-by-256) 110 = 125 khz (divide-by-64) 101 = 250 khz (divide-by-32) 100 = 500 khz (divide-by-16) 011 = 1 mhz (divide-by-8) 010 = 2 mhz (divide-by-4) 001 = 4 mhz (divide-by-2) 000 = 8 mhz (divide-by-1) bit 7-6 cpdiv<1:0>: system clock select bits (postscaler select from 32 mhz clock branch) 11 = 4 mhz (divide-by-8) (2) 10 = 8 mhz (divide-by-4) (2) 01 = 16 mhz (divide-by-2) 00 = 32 mhz (divide-by-1) bit 5 pllen: 96 mhz pll enable bit the 96 mhz pll must be enabled when the usb module is enabled. this control bit can be overridden by the pll96mhz (configuration word 2 <11>) configuration bit. 1 = enable the 96 mhz pll for usb or hspll/ecpll/frcpll operation 0 = disable the 96 mhz pll bit 4 reserved: reserved bit; do not use bit 3-0 unimplemented: read as ? 0 ? note 1: this bit is automatically cleared when the roi bit is set and an interrupt occurs. 2: this setting is not allowed while the usb module is enabled.
pic24fj256gb210 family ds39975a-page 142 ? 2010 microchip technology inc. register 8-3: osctun: frc oscillator tune register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 (1) tun4 (1) tun3 (1) tun2 (1) tun1 (1) tun0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 011111 = maximum frequency deviation 011110 = 000001 = 000000 = center frequency, oscillator is running at factory calibrated frequency 111111 = 100001 = 100000 = minimum frequency deviation note 1: increments or decrements of tun<5:0> may not change the frc frequency in equal steps over the frc tuning range and may not be monotonic.
? 2010 microchip technology inc. ds39975a-page 143 pic24fj256gb210 family 8.4 clock switching operation with few limitations, applications are free to switch between any of the four clock sources (posc, sosc, frc and lprc) under software control and at any time. to limit the possible side effects that could result from this flexibility, pic24f devices have a safeguard lock built into the switching process. 8.4.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in cw2 must be programmed to ? 0 ?. (refer to section 26.1 ?configuration bits? for further details.) if the fcksm1 configuration bit is unprogrammed (? 1 ?), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the noscx (osccon<10:8>) control bits do not control the clock selection when clock switching is disabled. however, the coscx (osccon<14:12>) control bits will reflect the clock source selected by the fnoscx configuration bits. the oswen (osccon<0>) control bit has no effect when clock switching is disabled; it is held at ? 0 ? at all times. 8.4.2 oscillator switching sequence at a minimum, performing a clock switch requires this basic sequence: 1. if desired, read the coscx (osccon<14:12>) control bits to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the noscx (osccon<10:8>) control bits for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the coscx bits with the new value of the noscx bits. if they are the same, then the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and cf (osccon<3>) bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware will wait until the ost expires. if the new source is using the pll, then the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the noscx bit values are transferred to the coscx bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled) or sosc (if soscen remains set). note: the primary oscillator mode has three different submodes (xt, hs and ec) which are determined by the poscmdx configuration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. note 1: the processor will continue to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any primary oscillator mode with pll and frcpll modes are not permitted. this applies to clock switches in either direc- tion. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes.
pic24fj256gb210 family ds39975a-page 144 ? 2010 microchip technology inc. a recommended code sequence for a clock switch includes the following: 1. disable interrupts during the osccon register unlock and write sequence. 2. execute the unlock sequence for the osccon high byte by writing 78h and 9ah to osccon<15:8> in two back-to-back instructions. 3. write new oscillator source to the noscx bits in the instruction immediately following the unlock sequence. 4. execute the unlock sequence for the osccon low byte by writing 46h and 57h to osccon<7:0> in two back-to-back instructions. 5. set the oswen bit in the instruction immediately following the unlock sequence. 6. continue to execute code that is not clock-sensitive (optional). 7. invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or pll to start and stabilize. 8. check to see if oswen is ? 0 ?. if it is, the switch was successful. if oswen is still set, then check the lock bit to determine the cause of failure. the core sequence for unlocking the osccon register and initiating a clock switch is shown in example 8-1. example 8-1: basic code sequence for clock switching in assembly 8.5 96 mhz pll block the 96 mhz pll block is implemented to generate the stable 48 mhz clock required for full-speed usb operation and the system clock from the same oscillator source. the 96 mhz pll block is shown in figure 8-2. the 96 mhz pll block requires a 4 mhz input signal; it uses this to generate a 96 mhz signal from a fixed, 24x pll. this is, in turn, divided into two branches. the first branch generates the usb clock and the second branch generates the system clock. the 96 mhz pll block can be enabled and disabled using the pll96mhz configu- ration bit (configuration word<11>) or through the pllen (clkdiv<5>) control bit when the pll96mhz configuration bit is not set. note that the pll96mhz configuration bit and pllen r egister bit are available only for pic24f devices with usb. the 96 mhz pll prescaler does not automatically sense the incoming oscillator frequency. the user must manually configure the pll divider to generate the required 4 mhz output, using the plldiv<2:0> config- uration bits (configuration word 2<14:12> in most devices). ;place the new oscillator selection in w0 ;oscconh (high byte) unlock sequence mov #oscconh, w1 mov #0x78, w2 mov #0x9a, w3 mov.b w2, [w1] mov.b w3, [w1] ;set new oscillator selection mov.b wreg, oscconh ;oscconl (low byte) unlock sequence mov #oscconl, w1 mov #0x46, w2 mov #0x57, w3 mov.b w2, [w1] mov.b w3, [w1] ;start oscillator switch operation bset osccon,#0
? 2010 microchip technology inc. ds39975a-page 145 pic24fj256gb210 family figure 8-2: 96 mhz pll block 8.5.1 system clock generation the system clock is generated from the 96 mhz branch using a configurable postscaler/divider to generate a range of frequencies for the system clock multiplexer. the output of the multiplexer is further passed through a fixed divide-by-3 divider and the final output is used as the system clock. figure 8-2 shows this logic in the system clock sub-block. since the source is a 96 mhz signal, the possible system clock frequencies are listed in table 8-2. the available system clock options are always the same, regardless of the setting of the plldiv configuration bits. table 8-2: system clock options for 96 mhz pll block pll 96 mhz pll ? 3 ? 2 prescaler 4 mhz pll prescaler 48 mhz clock for usb module pll output for system clock cpdiv<1:0> plldiv<2:0> input from posc input from frc fnosc<2:0> (4 mhz or 8 mhz) 00 01 10 11 32 mhz 111 110 101 100 011 010 001 000 ? 12 ? 8 ? 8 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 4 ? 2 ? 1 mcu clock division (cpdiv<1:0>) system clock frequency (instruction rate in mips) none ( 00 )32mhz (16) ? 2 ( 01 )16mhz (8) ? 4 ( 10 )8mhz (4) (1) ? 8 ( 11 )4mhz (2) (1) note 1: these options are not compatible with usb operation. they may be used whenever the pll branch is selected and the usb module is disabled.
pic24fj256gb210 family ds39975a-page 146 ? 2010 microchip technology inc. 8.5.2 usb clock generation in the usb-on-the-go module in the pic24fj256gb210 family of devices, the primary oscillator with the pll block can be used as a valid clock source for usb operation. the frc oscillator (implemented with 1.0% accuracy) can be combined with a pll block, providing another option for a valid usb clock source. there is no provision to provide a separate external 48 mhz clock to the usb module. the usb module sources its clock signal from a 96 mhz pll. due to the requirement that a 4 mhz input must be provided to generate the 96 mhz signal, the oscillator operation is limited to a range of possible val- ues. table 8-3 shows the valid oscillator configurations (i.e., ecpll, hspll, xtpll and frcpll) for usb operation. this sets the correct plldiv configuration for the specified oscillator frequency and the output frequency of the usb clock branch is always 48 mhz. table 8-3: valid oscillator conf igurations for usb operations input oscillator frequency clock mode pll division (plldiv<2:0>) 48 mhz ecpll ? 12 ( 111 ) 32 mhz hspll, ecpll ?? 8 ( 110 ) 24 mhz hspll, ecpll ? 6 ( 101 ) 20 mhz hspll, ecpll ? 5 ( 100 ) 16 mhz hspll, ecpll ? 4 ( 011 ) 12 mhz hspll, ecpll ? 3 ( 010 ) 8 mhz ecpll, hspll, xtpll, frcpll ? 2 ( 001 ) 4 mhz ecpll, hspll, xtpll, frcpll ? 1 ( 000 ) note: for usb devices, the use of a primary oscillator or external clock source, with a frequency above 32 mhz, does not imply that the device?s system clock can be run at the same speed when the usb module is not used. the maximum system clock for all pic24f devices is 32 mhz.
? 2010 microchip technology inc. ds39975a-page 147 pic24fj256gb210 family 8.5.3 considerations for usb operation when using the usb on-the-go module in pic24fj256gb210 family devices, users must always observe these rules in configuring the system clock: ? for usb operation, the selected clock source (ec, hs or xt) must meet the usb clock tolerance requirements. ? the primary oscillator/pll modes are the only oscillator configurations that permit usb opera- tion. there is no provision to provide a separate external clock source to the usb module. ? while the frcpll oscillator mode is used for usb applications, users must always ensure that the frc source is configured to provide a frequency of 4 mhz or 8 mhz (rcdiv<2:0> = 001 or 000 ) and that the usb pll prescaler is configured appropriately. all other oscillator modes are available; however, usb operation is not possible when these modes are selected. they may still be useful in cases where other power levels of operation are desirable and the usb module is not needed (e.g., the application is sleeping and waiting for a bus attachment). 8.6 reference clock output in addition to the clko output (f osc /2) available in certain oscillator modes, the device clock in the pic24fj256gb210 family devices can also be config- ured to provide a reference clock output signal to a port pin. this feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. this reference clock output is controlled by the refocon register (register 8-4). setting the roen bit (refocon<15>) makes the clock signal available on the refo pin. the rodiv bits (refocon<11:8>) enable the selection of 16 different clock divider options. the rosslp and rosel bits (refocon<13:12>) control the availability of the reference output during sleep mode. the rosel bit determines if the oscillator on osci and osco, or the current system clock source, is used for the reference clock output. the rosslp bit determines if the reference source is available on refo when the device is in sleep mode. to use the reference clock output in sleep mode, both the rosslp and rosel bits must be set. the device clock must also be configured for one of the primary modes (ec, hs or xt); otherwise, if the poscen bit is not also set, the oscillator on osci and osco will be powered down when the device enters sleep mode. clearing the rosel bit allows the reference output frequency to change as the system clock changes during any clock switches.
pic24fj256gb210 family ds39975a-page 148 ? 2010 microchip technology inc. register 8-4: refocon: reference oscillator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 roen ? rosslp rosel (1) rodiv3 rodiv2 rodiv1 rodiv0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roen: reference oscillator output enable bit 1 = reference oscillator is enabled on refo pin 0 = reference oscillator is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rosslp: reference oscillator output stop in sleep bit 1 = reference oscillator continues to run in sleep 0 = reference oscillator is disabled in sleep bit 12 rosel: reference oscillator source select bit (1) 1 = primary oscillator is used as the base clock 0 = system clock is used as the base clock; base clock reflects any clock switching of the device bit 11-8 rodiv<3:0>: reference oscillator divisor select bits 1111 = base clock value divided by 32,768 1110 = base clock value divided by 16,384 1101 = base clock value divided by 8,192 1100 = base clock value divided by 4,096 1011 = base clock value divided by 2,048 1010 = base clock value divided by 1,024 1001 = base clock value divided by 512 1000 = base clock value divided by 256 0111 = base clock value divided by 128 0110 = base clock value divided by 64 0101 = base clock value divided by 32 0100 = base clock value divided by 16 0011 = base clock value divided by 8 0010 = base clock value divided by 4 0001 = base clock value divided by 2 0000 = base clock value bit 7-0 unimplemented: read as ? 0 ? note 1: note that the crystal oscillator must be enabled using the fosc<2:0> bits; the crystal maintains the operation in sleep mode.
? 2010 microchip technology inc. ds39975a-page 149 pic24fj256gb210 family 9.0 power-saving features the pic24fj256gb210 family of devices provides the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. all pic24f devices manage power consumption in four different ways: ? clock frequency ? instruction-based sleep and idle modes ? software controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selectively tailor an application?s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 9.1 clock frequency and clock switching pic24f devices allow for a wide range of clock frequencies to be selected under application control. if the system clock configuratio n is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc bits. the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 8.0 ?oscillator configuration? . 9.2 instruction-based power-saving modes pic24f devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution; idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. the assembly syntax of the pwrsav instruction is shown in example 9-1. sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to ?wake-up?. 9.2.1 sleep mode sleep mode has these features: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption will be reduced to a minimum, provided that no i/o pin is sourcing current. ? the fail-safe clock monitor (fscm) does not operate during sleep mode since the system clock source is disabled. ? the lprc clock will continue to run in sleep mode if the wdt is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features or peripherals may continue to operate in sleep mode. this includes items such as the input change notification on the i/o ports or peripherals that use an external clock input. any peripheral that requires the system clock source for its operation will be disabled in sleep mode. users can opt to make the voltage regulator enter standby mode on entering sleep mode by clearing the vregs bit (rcon<8>). this will decrease current consumption but will add a delay, t vreg , to the wake-up time. for this reason, applications that do not use the voltage regulator should set this bit. the device will wake-up from sleep mode on any of these events: ? on any interrupt source that is individually enabled ? on any form of device reset ? on a wdt time-out on wake-up from sleep, the processor will restart with the same clock source that was active when sleep mode was entered. example 9-1: pwrsav instruction syntax note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 10. ?power-saving features? (ds39698). the information in this data sheet supersedes the information in the frm. pwrsav #0 ; put the device into sleep mode pwrsav #1 ; put the device into idle mode
pic24fj256gb210 family ds39975a-page 150 ? 2010 microchip technology inc. 9.2.2 idle mode idle mode has these features: ? the cpu will stop executing instructions. ? the wdt is automatically cleared. ? the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 9.4 ?selective peripheral module control? ). ? if the wdt or fscm is enabled, the lprc will also remain active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled. ? any device reset. ? a wdt time-out. on wake-up from idle, the clock is reapplied to the cpu and instruction execution begins immediately, starting with the instruction following the pwrsav instruction or the first instruction in the isr. 9.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction will be held off until entry into sleep or idle mode has completed. the device will then wake-up from sleep or idle mode. 9.3 doze mode generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. there may be cir- cumstances, however, where this is not practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock contin- ues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. it is also possible to use doze mode to selectively reduce power consumption in event driven applica- tions. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. enabling the automatic return to full-speed cpu operation on interrupts is enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. 9.4 selective peripheral module control idle and doze modes allow users to substantially reduce power consumption by slowing or stopping the cpu clock. even so, peripheral modules still remain clocked, and thus, consume power. there may be cases where the application needs what these modes do not provide: the allocation of power resources to cpu processing with minimal power consumption from the peripherals. pic24f devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. this can be done with two control bits: ? the peripheral enable bit, generically named, ?xxxen?, located in the module?s main control sfr. ? the peripheral module disable (pmd) bit, generically named, ?xxxmd?, located in one of the pmd control registers. both bits have similar functions in enabling or disabling its associated module. setting the pmd bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. in this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. many peripheral modules have a corresponding pmd bit. in contrast, disabling a module by clearing its xxxen bit disables its functionality, but leaves its registers available to be read and written to. this reduces power consumption, but not by as much as setting the pmd bit does. most peripheral modules have an enable bit; exceptions include input capture, output compare and rtcc. to achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters idle mode. this is done through the control bit of the generic name format, ?xxxidl?. by default, all modules that can operate during idle mode will do so. using the disable on idle feature allows further reduction of power consumption during idle mode, enhancing power savings for extremely critical power applications.
? 2010 microchip technology inc. ds39975a-page 151 pic24fj256gb210 family 10.0 i/o ports all of the device pins (except v dd , v ss , mclr and osci/clki) are shared between the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger (st) inputs for improved noise immunity. 10.1 parallel i/o (pio) ports a parallel i/o port that shares a pin with a peripheral is, in general, subservient to the peripheral. the periph- eral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through?, in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 10-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and it is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin may be read, but the output driver for the parallel port bit will be disabled. if a peripheral is enabled, but it is not actively driving a pin, that pin may be driven by a port. all port pins have three registers directly associated with their operation as digital i/o and one register asso- ciated with their operation as analog input. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the output latch reg- ister (latx), read the latch; writes to the latch, write the latch. reads from the port (portx), read the port pins; writes to the port pins, write to the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers, and the port pin will read as zeros. when a pin is shared with another peripheral or func- tion that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of inputs. figure 10-1: block diag ram of a typical shared port structure note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 12. ?i/o ports with peripheral pin select (pps)? (ds39711). the infor- mation in this data sheet supersedes the information in the frm. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat
pic24fj256gb210 family ds39975a-page 152 ? 2010 microchip technology inc. 10.1.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically, this instruction would be a nop . 10.1.2 open-drain configuration in addition to the port, lat and tris registers for data control, each port pin can also be individually configured for either a digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd (e.g., 5v) on any desired digital only pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. 10.1.3 configuring d+ and d- pins (rg2 and rg3) the input buffers of the rg2 and rg3 pins are, by default, tri-stated. to use these pins as input pins, the utrdis bit (u1cnfg2<0>) should be set, which enables the input buffers on these pins. 10.2 configuring analog port pins (ansel) the ansx and trisx registers control the operation of the pins with analog function. each port pin with analog function is associated with one of the ans bits (see register 10-1 through register 10-7), which decides if the pin function should be analog or digital. refer to table 10-1 for detailed behavior of the pin for different ansx and trisx bit settings. when reading the port register, all pins configured as analog input channels will read as cleared (a low level). 10.2.1 analog input pins and voltage considerations the voltage tolerance of pins used as device inputs is dependent on the pin?s input function. pins that are used as digital only inputs are able to handle dc voltages of up to 5.5v, a level typical for digital logic circuits. in contrast, pins that also have analog input functions of any kind can only tolerate voltages up to v dd . voltage excursions beyond v dd on these pins should always be avoided. table 10-2 summarizes the input capabilities. refer to section 29.1 ?dc characteristics? for more details. table 10-1: configuring analog/d igital function of an i/o pin pin function ansx setting trisx setting comments analog input 11 it is recommended to keep ansx = 1 . analog output 11 it is recommended to keep ansx = 1 . digital input 01 firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. digital output 00 make sure to disable the analog output function on the pin if any is present. table 10-2: input voltage levels for po rt or pin tolerated description input port or pin tolerated input description porta (1) <10:9, 7:6> v dd only v dd input levels are tolerated. portb<15:0> portc (1) <15:12, 4> portd<7:6> porte (1) <9> portf<0> portg<9:6, 3:2> porta (1) <15:14, 5:0> 5.5v tolerates input levels above v dd , useful for most standard logic. portc (1) <3:1> portd (1) <15:8, 5:0> porte (1) <8:0> portf (1) <13:12, 8:7, 5:1> portg (1) <15:12, 1:0> note 1: not all of the pins of these ports are implemented in 64-pin devices (pic24fjxxxgb206); refer to the device pinout diagrams for the details.
? 2010 microchip technology inc. ds39975a-page 153 pic24fj256gb210 family register 10-1: ansa: porta analog function selection register (1) u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 u-0 ? ? ? ? ? ansa10 ansa9 ? bit 15 bit 8 r/w-1 r/w-1 u-0 u-0 u-0 u-0 u-0 u-0 ansa7 ansa6 ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 ansa<10:9>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 8 unimplemented: read as ? 0 ? bit 7-6 ansa<7:6>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 5-0 unimplemented: read as ? 0 ? note 1: this register is not available on 64-pin devices (pic24fjxxxgb206).
pic24fj256gb210 family ds39975a-page 154 ? 2010 microchip technology inc. register 10-2: ansb: portb analog function selection register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansb15 ansb14 ansb13 ansb12 ansb11 ansb10 ansb9 ansb8 bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ansb7 ansb6 ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 ansb<15:0>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled register 10-3: ansc: portc analog function selection register u-0 r/w-1 r/w-1 u-0 u-0 u-0 u-0 u-0 ? ansc14 ansc13 ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 u-0 u-0 u-0 u-0 ? ? ? ansc4 (1) ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-13 ansc<14:13>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 12-5 unimplemented: read as ? 0 ? bit 4 ansc4: analog function selection bit (1) 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 3-0 unimplemented: read as ? 0 ? note 1: this bit is not available on 64-pin devices (pic24fjxxxgb206).
? 2010 microchip technology inc. ds39975a-page 155 pic24fj256gb210 family register 10-4: ansd: portd analog function selection register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-1 r/w-1 u-0 u-0 u-0 u-0 u-0 u-0 ansd7 ansd6 ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-6 ansd<7:6>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 5-0 unimplemented: read as ? 0 ? register 10-5: anse: porte anal og function selection register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 u-0 ? ? ? ? ? ? anse9 ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9 anse9: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 8-0 unimplemented: read as ? 0 ? note 1: this register is not available in 64-pin devices (pic24fjxxxgb206).
pic24fj256gb210 family ds39975a-page 156 ? 2010 microchip technology inc. register 10-6: ansf: portf anal og function selection register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 ? ? ? ? ? ? ?ansf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 unimplemented: read as ? 0 ? bit 0 ansf0: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled register 10-7: ansg: portg anal og function selection register u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 ? ? ? ? ? ? ansg9 ansg8 bit 15 bit 8 r/w-1 r/w-1 u-0 u-0 u-0 u-0 u-0 u-0 ansg7 ansg6 ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-6 ansg<9:6>: analog function selection bits 1 = pin is configured in analog mode; i/o port read is disabled 0 = pin is configured in digital mode; i/o port read is enabled bit 5-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 157 pic24fj256gb210 family 10.3 input change notification the input change notification function of the i/o ports allows the pic24fj256gb210 family of devices to gen- erate interrupt requests to the processor in response to a change-of-state (cos) on selected input pins. this feature is capable of detecting input change-of-states, even in sleep mode, when the clocks are disabled. depending on the device pin count, there are up to 84 external inputs that may be selected (enabled) for generating an interrupt request on a change-of-state. registers, cnen1 through cnen6, contain the inter- rupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin has a both a weak pull-up and a weak pull-down connected to it. the pull-ups act as a current source that is connected to the pin, while the pull-downs act as a current sink that is connected to the pin. these eliminate the need for external resistors when push button or keypad devices are connected. the pull-ups and pull-downs are separately enabled using the cnpu1 through cnpu6 registers (for pull-ups), and the cnpd1 through cnpd6 registers (for pull-downs). each cn pin has individual control bits for its pull-up and pull-down. setting a control bit enables the weak pull-up or pull-down for the corresponding pin. when the internal pull-up is selected, the pin pulls up to v dd ? 1.1v (typical). when the internal pull-down is selected, the pin pulls down to v ss . example 10-1: port write/read in assembly example 10-2: port write/read in ?c? note: pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. note: to use cn83 and cn84, which are on the d+ and d- pins, the utrdis bit (u1cnfg2<0>) should be set. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction trisb = 0xff00; //configure portb<15:8> as inputs and portb<7:0> as outputs nop(); //delay 1 cycle if (portbbits.rb13) { }; //next instruction
pic24fj256gb210 family ds39975a-page 158 ? 2010 microchip technology inc. 10.4 peripheral pin select (pps) a major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. in an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option. the peripheral pin select (pps) feature provides an alternative to these choices by enabling the user?s peripheral set selection and its placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select feature operates over a fixed subset of digital i/o pins. users may independently map the input and/or output of any one of many digital peripherals to any one of these i/o pins. pps is per- formed in software and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 10.4.1 available pins the pps feature is used with a range of up to 44 pins, depending on the particular device and its pin count. pins that support the peripheral pin select feature include the designation, ?rpn? or ?rpin?, in their full pin designation, where ?n? is the remappable pin number. ?rp? is used to designate pins that support both remap- pable input and output functions, while ?rpi? indicates pins that support remappable input functions only. pic24fj256gb210 family devices support a larger number of remappable input only pins than remappable input/output pins. in this device family, there are up to 32 remappable input/output pins, depending on the pin count of the particular device selected; these are num- bered, rp0 through rp31. remappable input only pins are numbered above this range, from rpi32 to rpi43 (or the upper limit for that particular device). see table 1-1 for a summary of pinout options in each package offering. 10.4.2 available peripherals the peripherals managed by the pps are all digital only peripherals. these include general serial commu- nications (uart and spi), general purpose timer clock inputs, timer related peripherals (input capture and out- put compare) and external interrupt inputs. also included are the outputs of the comparator module, since these are discrete digital signals. pps is not available for i 2 c, change notification inputs, rtcc alarm outputs, epmp signals or peripherals with analog inputs. a key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.4.2.1 peripheral pin select function priority pin-selectable peripheral outputs (e.g., oc, uart transmit) will take priority over general purpose digital functions on a pin, such as epmp and port i/o. special- ized digital outputs, such as usb functionality, will take priority over pps outputs on the same pin. the pin diagrams list peripheral outputs in the order of priority. refer to them for priority concerns on a particular pin. unlike pic24f devices with fixed peripherals, pin-selectable peripheral inputs will never take owner- ship of a pin. the pin?s output buffer will be controlled by the trisx setting or by a fixed peripheral on the pin. if the pin is configured in digital mode then the pps input will operate correctly. if an analog function is enabled on the pin, the pps input will be disabled. 10.4.3 controlling peripheral pin select pps features are controlled through two sets of special function registers (sfrs): one to map peripheral inputs and one to map outputs. because they are separately controlled, a particular peripheral?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped. 10.4.3.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 10-8 through register 10-28). each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripherals. programming a given peripheral?s bit field with an appropriate 6-bit value maps the rpn/rpin pin with that value to that peripheral. for any given device, the valid range of values for any of the bit fields corresponds to the max- imum number of peripheral pin selections supported by the device.
? 2010 microchip technology inc. ds39975a-page 159 pic24fj256gb210 family table 10-3: selectable input sources (maps input to function) (1) input name function name register function mapping bits external interrupt 1 int1 rpinr0 int1r<5:0> external interrupt 2 int2 rpinr1 int2r<5:0> external interrupt 3 int3 rpinr1 int3r<5:0> external interrupt 4 int4 rpinr2 int4r<5:0> input capture 1 ic1 rpinr7 ic1r<5:0> input capture 2 ic2 rpinr7 ic2r<5:0> input capture 3 ic3 rpinr8 ic3r<5:0> input capture 4 ic4 rpinr8 ic4r<5:0> input capture 5 ic5 rpinr9 ic5r<5:0> input capture 6 ic6 rpinr9 ic6r<5:0> input capture 7 ic7 rpinr10 ic7r<5:0> input capture 8 ic8 rpinr10 ic8r<5:0> input capture 9 ic9 rpinr15 ic9r<5:0> output compare fault a ocfa rpinr11 ocfar<5:0> output compare fault b ocfb rpinr11 ocfbr<5:0> spi1 clock input sck1in rpinr20 sck1r<5:0> spi1 data input sdi1 rpinr20 sdi1r<5:0> spi1 slave select input ss1in rpinr21 ss1r<5:0> spi2 clock input sck2in rpinr22 sck2r<5:0> spi2 data input sdi2 rpinr22 sdi2r<5:0> spi2 slave select input ss2in rpinr23 ss2r<5:0> spi3 clock input sck3in rpinr28 sck3r<5:0> spi3 data input sdi3 rpinr28 sdi3r<5:0> spi3 slave select input ss3in rpinr29 ss3r<5:0> timer2 external clock t2ck rpinr3 t2ckr<5:0> timer3 external clock t3ck rpinr3 t3ckr<5:0> timer4 external clock t4ck rpinr4 t4ckr<5:0> timer5 external clock t5ck rpinr4 t5ckr<5:0> uart1 clear to send u1cts rpinr18 u1ctsr<5:0> uart1 receive u1rx rpinr18 u1rxr<5:0> uart2 clear to send u2cts rpinr19 u2ctsr<5:0> uart2 receive u2rx rpinr19 u2rxr<5:0> uart3 clear to send u3cts rpinr21 u3ctsr<5:0> uart3 receive u3rx rpinr17 u3rxr<5:0> uart4 clear to send u4cts rpinr27 u4ctsr<5:0> uart4 receive u4rx rpinr27 u4rxr<5:0> note 1: unless otherwise noted, all inputs use the schmitt trigger (st) input buffers.
pic24fj256gb210 family ds39975a-page 160 ? 2010 microchip technology inc. 10.4.3.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. each register contains two 6-bit fields, with each field being associated with one rpn pin (see register 10-29 through register 10-44). the value of the bit field corresponds to one of the peripherals and that peripheral?s output is mapped to the pin (see table 10-4). because of the mapping technique, the list of peripher- als for output mapping also includes a null value of ? 000000 ?. this permits any given pin to remain discon- nected from the output of any of the pin-selectable peripherals. table 10-4: selectable output so urces (maps function to output) output function number (1) function output name 0 null (2) null 1 c1out comparator 1 output 2 c2out comparator 2 output 3 u1tx uart1 transmit 4u1rts (3) uart1 request to send 5 u2tx uart2 transmit 6u2rts (3) uart2 request to send 7 sdo1 spi1 data output 8 sck1out spi1 clock output 9 ss1out spi1 slave select output 10 sdo2 spi2 data output 11 sck2out spi2 clock output 12 ss2out spi2 slave select output 18 oc1 output compare 1 19 oc2 output compare 2 20 oc3 output compare 3 21 oc4 output compare 4 22 oc5 output compare 5 23 oc6 output compare 6 24 oc7 output compare 7 25 oc8 output compare 8 28 u3tx uart3 transmit 29 u3rts (3) uart3 request to send 30 u4tx uart4 transmit 31 u4rts (3) uart4 request to send 32 sdo3 spi3 data output 33 sck3out spi3 clock output 34 ss3out spi3 slave select output 35 oc9 output compare 9 36 c3out comparator 3 output 37-63 (unused) nc note 1: setting the rporx register with the listed value assigns that output function to the associated rpn pin. 2: the null function is assigned to all rpn outputs at device reset and disables the rpn output function. 3: irda ? bclk functionality uses this output.
? 2010 microchip technology inc. ds39975a-page 161 pic24fj256gb210 family 10.4.3.3 mapping limitations the control schema of the peripheral pin select is extremely flexible. other than systematic blocks that prevent signal contention, caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts. the flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 10.4.3.4 mapping exceptions for pic24fj256gb210 devices although the pps registers theoretically allow for up to 64 remappable i/o pins, not all of these are imple- mented in all devices. for pic24fj256gb210 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. in addition, some pins in the rp and rpi sequences are unimplemented in lower pin count devices. the differences in available remappable pins are summarized in table 10-5. when developing applications that use remappable pins, users should also keep these things in mind: ? for the rpinrx registers, bit combinations corre- sponding to an unimplemented pin for a particular device are treated as invalid. the corresponding module will not have an input mapped to it. for all pic24fj256gb210 family devices, this includes all values greater than 43 (? 101011 ?). ? for rporx registers, the bit fields corresponding to an unimplemented pin will also be unimple- mented. writing to these fields will have no effect. 10.4.4 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic24f devices include three features to prevent alterations to the peripheral map: ? control register lock sequence ? continuous state monitoring ? configuration bit remapping lock 10.4.4.1 control register lock under normal operation, writes to the rpinrx and rporx registers are not allowed. attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. to change these reg- isters, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 46h to osccon<7:0>. 2. write 57h to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillator?s lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.4.4.2 continuous state monitoring in addition to being protected from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 10.4.4.3 configuration bit pin select lock as an additional level of safety, the device can be con- figured to prevent more than one write session to the rpinrx and rporx registers. the iol1way (cw2<4>) configuration bit blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure will not execute and the peripheral pin select control reg- isters cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. programming iol1way allows users unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. table 10-5: remappable pin exceptions for pic24fj256gb210 family devices device pin count rp pins (i/o) rpi pins total unimplemented total unimplemented 64-pin (pic24fjxxxgb206) 28 rp5, rp15, rp30, rp31 1 rpi32-36, rpi38-43 100/121-pin (pic24fjxxxgb210) 32 ? 12 ?
pic24fj256gb210 family ds39975a-page 162 ? 2010 microchip technology inc. 10.4.5 considerations for peripheral pin selection the ability to control peripheral pin selection intro- duces several considerations into application design that could be overlooked. this is particularly true for several common peripherals that are available only as remappable peripherals. the main consideration is that the peripheral pin selects are not available on default pins in the device?s default (reset) state. since all rpinrx registers reset to ? 111111 ? and all rporx registers reset to ? 000000 ?, all peripheral pin select inputs are tied to v ss and all peripheral pin select outputs are disconnected. this situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. since the iolock bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of reset. for application safety, however, it is best to set iolock and lock the configuration after writing to the control registers. because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configura- tion. if the bulk of the application is written in ?c?, or another high-level language, the unlock sequence should be performed by writing in-line assembly. choosing the configuration requires the review of all peripheral pin selects and their pin assignments, especially those that will not be used in the application. in all cases, unused pin-selectable peripherals should be disabled completely. unused peripherals should have their inputs assigned to an unused rpn/rpin pin function. i/o pins with unused rpn functions should be configured with the null peripheral output. the assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin?s i/o circuitry. in theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. to be safe, fixed digital peripherals that share the same pin should be disabled when not in use. along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. the peripheral must be specifically config- ured for operation, and enabled as if it were tied to a fixed pin. where this happens in the application code (immedi- ately following device reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. a final consideration is that peripheral pin select func- tions neither override analog inputs nor reconfigure pins with analog functions for digital i/o. if a pin is configured as an analog input on device reset, it must be explicitly reconfigured as digital i/o when used with a peripheral pin select. example 10-3 shows a configuration for bidirectional communication with flow control using uart1. the following input and output functions are used: ? input functions: u1rx, u1cts ? output functions: u1tx, u1rts example 10-3: conf iguring uart1 input and output functions note: in tying peripheral pin select inputs to rp63, rp63 need not exist on a device for the registers to be reset to it. // unlock registers asm volatile( "mov #osccon, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, [w1] \n" "mov.b w3, [w1] \n" "bclr osccon,#6"); // or use c30 built-in macro: // _builtin_write_oscconl (osccon & 0xbf); // configure input functions (table table 10-2)) // assign u1rx to pin rp0 rpinr18bits.u1rxr = 0; // assign u1cts to pin rp1 rpinr18bits.u1ctsr = 1; // configure output functions (table 10-4) // assign u1tx to pin rp2 rpor1bits.rp2r = 3; // assign u1rts to pin rp3 rpor1bits.rp3r = 4; // lock registers asm volatile ("mov #osccon, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, [w1]\ n" "mov.b w3, [w1] \n" "bset osccon, #6") ; // or use c30 built-in macro: // _builtin_write_oscconl (osccon ? 0x40);
? 2010 microchip technology inc. ds39975a-page 163 pic24fj256gb210 family 10.4.6 peripheral pin select registers the pic24fj256gb210 family of devices implements a total of 37 registers for remappable peripheral configuration: ? input remappable peripheral registers (21) ? output remappable peripheral registers (16) note: input and output register values can only be changed if iolock (osccon<6>) = 0 . see section 10.4.4.1 ?control register lock? for a specific command sequence. register 10-8: rpinr0: peripheral pin select input register 0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? int1r5 int1r4 int1r3 int1r2 int1r1 int1r0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 int1r<5:0>: assign external interrupt 1 (int1) to the corresponding rpn or rpin pin bits bit 7-0 unimplemented: read as ? 0 ? register 10-9: rpinr1: peripheral pin select input register 1 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? int3r5 int3r4 int3r3 int3r2 int3r1 int3r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? int2r5 int2r4 int2r3 int2r2 int2r1 int2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 int3r<5:0>: assign external interrupt 3 (int3) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 int2r<5:0>: assign external interrupt 2 (int2) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 164 ? 2010 microchip technology inc. register 10-10: rpinr2: peripheral pin select input register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? int4r5 int4r4 int4r3 int4r2 int4r1 int4r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 int4r<5:0>: assign external interrupt 4 (int4) to the corresponding rpn or rpin pin bits register 10-11: rpinr3: peripheral pin select input register 3 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? t3ckr5 t3ckr4 t3ckr3 t3ckr2 t3ckr1 t3ckr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? t2ckr5 t2ckr4 t2ckr3 t2ckr2 t2ckr1 t2ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 t3ckr<5:0>: assign timer3 external clock (t3ck) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 t2ckr<5:0>: assign timer2 external clock (t2ck) to the corresponding rpn or rpin pin bits
? 2010 microchip technology inc. ds39975a-page 165 pic24fj256gb210 family register 10-12: rpinr4: peripheral pin select input register 4 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? t5ckr5 t5ckr4 t5ckr3 t5ckr2 t5ckr1 t5ckr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? t4ckr5 t4ckr4 t4ckr3 t4ckr2 t4ckr1 t4ckr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 t5ckr<5:0>: assign timer5 external clock (t5ck) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 t4ckr<5:0>: assign timer4 external clock (t4ck) to the corresponding rpn or rpin pin bits register 10-13: rpinr7: peripheral pin select input register 7 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic2r5 ic2r4 ic2r3 ic2r2 ic2r1 ic2r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic1r5 ic1r4 ic1r3 ic1r2 ic1r1 ic1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ic2r<5:0>: assign input capture 2 (ic2) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ic1r<5:0>: assign input capture 1 (ic1) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 166 ? 2010 microchip technology inc. register 10-14: rpinr8: peripheral pin select input register 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic4r5 ic4r4 ic4r3 ic4r2 ic4r1 ic4r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic3r5 ic3r4 ic3r3 ic3r2 ic3r1 ic3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ic4r<5:0>: assign input capture 4 (ic4) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ic3r<5:0>: assign input capture 3 (ic3) to the corresponding rpn or rpin pin bits register 10-15: rpinr9: peripheral pin select input register 9 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic6r5 ic6r4 ic6r3 ic6r2 ic6r1 ic6r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic5r5 ic5r4 ic5r3 ic5r2 ic5r1 ic5r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ic6r<5:0>: assign input capture 6 (ic6) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ic5r<5:0>: assign input capture 5 (ic5) to the corresponding rpn or rpin pin bits
? 2010 microchip technology inc. ds39975a-page 167 pic24fj256gb210 family register 10-16: rpinr10: peripheral pin select input register 10 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic8r5 ic8r4 ic8r3 ic8r2 ic8r1 ic8r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic7r5 ic7r4 ic7r3 ic7r2 ic7r1 ic7r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ic8r<5:0>: assign input capture 8 (ic8) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ic7r<5:0>: assign input capture 7 (ic7) to the corresponding rpn or rpin pin bits register 10-17: rpinr11: peripheral pin select input register 11 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ocfbr5 ocfbr4 ocfbr3 ocfbr2 ocfbr1 ocfbr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ocfar5 ocfar4 ocfar3 ocfar2 ocfar1 ocfar0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ocfbr<5:0>: assign output compare fault b (ocfb) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ocfar<5:0>: assign output compare fault a (ocfa) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 168 ? 2010 microchip technology inc. register 10-18: rpinr15: peripheral pin select input register 15 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ic9r5 ic9r4 ic9r3 ic9r2 ic9r1 ic9r0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 ic9r<5:0>: assign input capture 9 (ic9) to the corresponding rpn or rpin pin bits bit 7-0 unimplemented: read as ? 0 ? register 10-19: rpinr17: peripheral pin select input register 17 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u3rxr5 u3rxr4 u3rxr3 u3rxr2 u3rxr1 u3rxr0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 u3rxr<5:0>: assign uart3 receive (u3rx) to the corresponding rpn or rpin pin bits bit 7-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 169 pic24fj256gb210 family register 10-20: rpinr18: peripheral pin select input register 18 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u1ctsr5 u1ctsr4 u1ctsr3 u1ctsr2 u1ctsr1 u1ctsr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u1rxr5 u1rxr4 u1rxr3 u1rxr2 u1rxr1 u1rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 u1ctsr<5:0>: assign uart1 clear to send (u1cts ) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 u1rxr<5:0>: assign uart1 receive (u1rx) to the corresponding rpn or rpin pin bits register 10-21: rpinr19: peripheral pin select input register 19 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u2ctsr5 u2ctsr4 u2ctsr3 u2ctsr2 u2ctsr1 u2ctsr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u2rxr5 u2rxr4 u2rxr3 u2rxr2 u2rxr1 u2rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 u2ctsr<5:0>: assign uart2 clear to send (u2cts ) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 u2rxr<5:0>: assign uart2 receive (u2rx) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 170 ? 2010 microchip technology inc. register 10-22: rpinr20: peripheral pin select input register 20 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sck1r5 sck1r4 sck1r3 sck1r2 sck1r1 sck1r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sdi1r5 sdi1r4 sdi1r3 sdi1r2 sdi1r1 sdi1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 sck1r<5:0>: assign spi1 clock input (sck1in) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 sdi1r<5:0>: assign spi1 data input (sdi1) to the corresponding rpn or rpin pin bits register 10-23: rpinr21: peripheral pin select input register 21 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u3ctsr5 u3ctsr4 u3ctsr3 u3ctsr2 u3ctsr1 u3ctsr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ss1r5 ss1r4 ss1r3 ss1r2 ss1r1 ss1r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 u3ctsr<5:0>: assign uart3 clear to send (u3cts ) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ss1r<5:0>: assign spi1 slave select input (ss1in) to the corresponding rpn or rpin pin bits
? 2010 microchip technology inc. ds39975a-page 171 pic24fj256gb210 family register 10-24: rpinr22: peripheral pin select input register 22 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sck2r5 sck2r4 sck2r3 sck2r2 sck2r1 sck2r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sdi2r5 sdi2r4 sdi2r3 sdi2r2 sdi2r1 sdi2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 sck2r<5:0>: assign spi2 clock input (sck2in) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 sdi2r<5:0>: assign spi2 data input (sdi2) to the corresponding rpn or rpin pin bits register 10-25: rpinr23: peripheral pin select input register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ss2r5 ss2r4 ss2r3 ss2r2 ss2r1 ss2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 ss2r<5:0>: assign spi2 slave select input (ss2in) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 172 ? 2010 microchip technology inc. register 10-26: rpinr27: peripheral pin select input register 27 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u4ctsr5 u4ctsr4 u4ctsr3 u4ctsr2 u4ctsr1 u4ctsr0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? u4rxr5 u4rxr4 u4rxr3 u4rxr2 u4rxr1 u4rxr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 u4ctsr<5:0>: assign uart4 clear to send (u4cts) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 u4rxr<5:0>: assign uart4 receive (u4rx) to the corresponding rpn or rpin pin bits register 10-27: rpinr28: peripheral pin select input register 28 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sck3r5 sck3r4 sck3r3 sck3r2 sck3r1 sck3r0 bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? sdi3r5 sdi3r4 sdi3r3 sdi3r2 sdi3r1 sdi3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 sck3r<5:0>: assign spi3 clock input (sck3in) to the corresponding rpn or rpin pin bits bit 7-6 unimplemented: read as ? 0 ? bit 5-0 sdi3r<5:0>: assign spi3 data input (sdi3) to the corresponding rpn or rpin pin bits
? 2010 microchip technology inc. ds39975a-page 173 pic24fj256gb210 family register 10-28: rpinr29: peripheral pin select input register 29 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ss3r5 ss3r4 ss3r3 ss3r2 ss3r1 ss3r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 ss3r<5:0>: assign spi3 slave select input (ss31in) to the corresponding rpn or rpin pin bits
pic24fj256gb210 family ds39975a-page 174 ? 2010 microchip technology inc. register 10-29: rpor0: peripheral pin select output register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp1r5 rp1r4 rp1r3 rp1r2 rp1r1 rp1r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp0r5 rp0r4 rp0r3 rp0r2 rp0r1 rp0r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp1r<5:0>: rp1 output pin mapping bits peripheral output number n is assigned to pin, rp1 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp0r<5:0>: rp0 output pin mapping bits peripheral output number n is assigned to pin, rp0 (see table 10-4 for peripheral function numbers). register 10-30: rpor1: peripheral pin select output register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp3r5 rp3r4 rp3r3 rp3r2 rp3r1 rp3r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp2r5 rp2r4 rp2r3 rp2r2 rp2r1 rp2r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp3r<5:0>: rp3 output pin mapping bits peripheral output number n is assigned to pin, rp3 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp2r<5:0>: rp2 output pin mapping bits peripheral output number n is assigned to pin, rp2 (see table 10-4 for peripheral function numbers).
? 2010 microchip technology inc. ds39975a-page 175 pic24fj256gb210 family register 10-31: rpor2: peripheral pin select output register 2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ?rp5r5 (1) rp5r4 (1) rp5r3 (1) rp5r2 (1) rp5r1 (1) rp5r0 (1) bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp4r5 rp4r4 rp4r3 rp4r2 rp4r1 rp4r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp5r<5:0>: rp5 output pin mapping bits (1) peripheral output number n is assigned to pin, rp5 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp4r<5:0>: rp4 output pin mapping bits peripheral output number n is assigned to pin, rp4 (see table 10-4 for peripheral function numbers). note 1: unimplemented in 64-pin devices; read as ? 0 ?. register 10-32: rpor3: peripheral pin select output register 3 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp7r5 rp7r4 rp7r3 rp7r2 rp7r1 rp7r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp6r5 rp6r4 rp6r3 rp6r2 rp6r1 rp6r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp7r<5:0>: rp7 output pin mapping bits peripheral output number n is assigned to pin, rp7 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp6r<5:0>: rp6 output pin mapping bits peripheral output number n is assigned to pin, rp6 (see table 10-4 for peripheral function numbers).
pic24fj256gb210 family ds39975a-page 176 ? 2010 microchip technology inc. register 10-33: rpor4: peripheral pin select output register 4 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp9r5 rp9r4 rp9r3 rp9r2 rp9r1 rp9r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp8r5 rp8r4 rp8r3 rp8r2 rp8r1 rp8r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp9r<5:0>: rp9 output pin mapping bits peripheral output number n is assigned to pin, rp9 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp8r<5:0>: rp8 output pin mapping bits peripheral output number n is assigned to pin, rp8 (see table 10-4 for peripheral function numbers). register 10-34: rpor5: peripheral pin select output register 5 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp11r5 rp11r4 rp11r3 rp11r2 rp11r1 rp11r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp10r5 rp10r4 rp10r3 rp10r2 rp10r1 rp10r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp11r<5:0>: rp11 output pin mapping bits peripheral output number n is assigned to pin, rp11 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp10r<5:0>: rp10 output pin mapping bits peripheral output number n is assigned to pin, rp10 (see table 10-4 for peripheral function numbers).
? 2010 microchip technology inc. ds39975a-page 177 pic24fj256gb210 family register 10-35: rpor6: peripheral pin select output register 6 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp13r5 rp13r4 rp13r3 rp13r2 rp13r1 rp13r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp12r5 rp12r4 rp12r3 rp12r2 rp12r1 rp12r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp13r<5:0>: rp13 output pin mapping bits peripheral output number n is assigned to pin, rp13 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp12r<5:0>: rp12 output pin mapping bits peripheral output number n is assigned to pin, rp12 (see table 10-4 for peripheral function numbers). register 10-36: rpor7: peripheral pin select output register 7 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ?rp15r5 (1) rp15r4 (1) rp15r3 (1) rp15r2 (1) rp15r1 (1) rp15r0 (1) bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp14r5 rp14r4 rp14r3 rp14r2 rp14r1 rp14r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp15r<5:0>: rp15 output pin mapping bits (1) peripheral output number n is assigned to pin, rp0 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp14r<5:0>: rp14 output pin mapping bits peripheral output number n is assigned to pin, rp14 (see table 10-4 for peripheral function numbers). note 1: unimplemented in 64-pin devices; read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 178 ? 2010 microchip technology inc. register 10-37: rpor8: peripheral pin select output register 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp17r5 rp17r4 rp17r3 rp17r2 rp17r1 rp17r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp16r5 rp16r4 rp16r3 rp16r2 rp16r1 rp16r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp17r<5:0>: rp17 output pin mapping bits peripheral output number n is assigned to pin, rp17 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp16r<5:0>: rp16 output pin mapping bits peripheral output number n is assigned to pin, rp16 (see table 10-4 for peripheral function numbers). register 10-38: rpor9: peripheral pin select output register 9 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp19r5 rp19r4 rp19r3 rp19r2 rp19r1 rp19r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp18r5 rp18r4 rp18r3 rp18r2 rp18r1 rp18r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp19r<5:0>: rp19 output pin mapping bits peripheral output number n is assigned to pin, rp19 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp18r<5:0>: rp18 output pin mapping bits peripheral output number n is assigned to pin, rp18 (see table 10-4 for peripheral function numbers).
? 2010 microchip technology inc. ds39975a-page 179 pic24fj256gb210 family register 10-39: rpor10: peripheral pin select output register 10 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp21r5 rp21r4 rp21r3 rp21r2 rp21r1 rp21r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp20r5 rp20r4 rp20r3 rp20r2 rp20r1 rp20r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp21r<5:0>: rp21 output pin mapping bits peripheral output number n is assigned to pin, rp21 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp20r<5:0>: rp20 output pin mapping bits peripheral output number n is assigned to pin, rp20 (see table 10-4 for peripheral function numbers). register 10-40: rpor11: peripheral pin select output register 11 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp23r5 rp23r4 rp23r3 rp23r2 rp23r1 rp23r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp22r5 rp22r4 rp22r3 rp22r2 rp22r1 rp22r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp23r<5:0>: rp23 output pin mapping bits peripheral output number n is assigned to pin, rp23 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp22r<5:0>: rp22 output pin mapping bits peripheral output number n is assigned to pin, rp22 (see table 10-4 for peripheral function numbers).
pic24fj256gb210 family ds39975a-page 180 ? 2010 microchip technology inc. register 10-41: rpor12: peripheral pin select output register 12 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp25r5 rp25r4 rp25r3 rp25r2 rp25r1 rp25r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp24r5 rp24r4 rp24r3 rp24r2 rp24r1 rp24r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp25r<5:0>: rp25 output pin mapping bits peripheral output number n is assigned to pin, rp25 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp24r<5:0>: rp24 output pin mapping bits peripheral output number n is assigned to pin, rp24 (see table 10-4 for peripheral function numbers). register 10-42: rpor13: peripheral pin select output register 13 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp27r5 rp27r4 rp27r3 rp27r2 rp27r1 rp27r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp26r5 rp26r4 rp26r3 rp26r2 rp26r1 rp26r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp27r<5:0>: rp27 output pin mapping bits peripheral output number n is assigned to pin, rp27 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp26r<5:0>: rp26 output pin mapping bits peripheral output number n is assigned to pin, rp26 (see table 10-4 for peripheral function numbers).
? 2010 microchip technology inc. ds39975a-page 181 pic24fj256gb210 family register 10-43: rpor14: peripheral pin select output register 14 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp29r5 rp29r4 rp29r3 rp29r2 rp29r1 rp29r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp28r5 rp28r4 rp28r3 rp28r2 rp28r1 rp28r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp29r<5:0>: rp29 output pin mapping bits peripheral output number n is assigned to pin, rp29 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp28r<5:0>: rp28 output pin mapping bits peripheral output number n is assigned to pin, rp28 (see table 10-4 for peripheral function numbers). register 10-44: rpor15: peripheral pin select output register 15 (1) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp31r5 rp31r4 rp31r3 rp31r2 rp31r1 rp31r0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rp30r5 rp30r4 rp30r3 rp30r2 rp30r1 rp30r0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 rp31r<5:0>: rp31 output pin mapping bits (1) peripheral output number n is assigned to pin, rp31 (see table 10-4 for peripheral function numbers). bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rp30r<5:0>: rp30 output pin mapping bits (1) peripheral output number n is assigned to pin, rp30 (see table 10-4 for peripheral function numbers). note 1: unimplemented in 64-pin devices; read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 182 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 183 pic24fj256gb210 family 11.0 timer1 the timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock (rtc) or operate as a free-running, interval timer/counter. timer1 can operate in three modes: ?16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 11-1 presents a block diagram of the 16-bit timer module. to configure timer1 for operation: 1. set the ton bit (= 1 ). 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. set or clear the tsync bit to configure synchronous or asynchronous operation. 5. load the timer period value into the pr1 register. 6. if interrupts are required, set the interrupt enable bit, t1ie. use the priority bits, t1ip<2:0>, to set the interrupt priority. figure 11-1: 16-bit timer1 module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 14. ?timers? (ds39704) . the information in this data sheet supersedes the information in the frm. ton sync sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q qd ck tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1x 01 tgate 00 gate sync
pic24fj256gb210 family ds39975a-page 184 ? 2010 microchip technology inc. register 11-1: t1con: timer1 control register (1) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps1 tckps0 ? tsync tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from t1ck pin (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: changing the value of txcon while the timer is running (ton = 1 ) causes the timer prescale counter to reset and is not recommended.
? 2010 microchip technology inc. ds39975a-page 185 pic24fj256gb210 family 12.0 timer2/3 and timer4/5 the timer2/3 and timer4/5 modules are 32-bit timers, which can also be configured as four independent, 16-bit timers with selectable operating modes. as 32-bit timers, timer2/3 and timer4/5 can each operate in three modes: ? two independent 16-bit timers with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer ? single 32-bit synchronous counter they also support these features: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? adc event trigger (only on timer2/3 in 32-bit mode and timer3 in 16-bit mode) individually, all four of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above except for the adc event trigger. the trigger is implemented only on timer2/3 in 32-bit mode and timer3 in 16-bit mode. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con and t5con registers. t2con and t4con are shown in generic form in register 12-1; t3con and t5con are shown in generic form register 12-2. for 32-bit timer/counter operation, timer2 and timer4 are the least significant word; timer3 and timer4 are the most significant word of the 32-bit timers. to configure timer2/3 or timer4/5 for 32-bit operation: 1. set the t32 bit (t2con<3> or t4con<3> = 1 ). 2. select the prescaler ratio for timer2 or timer4 using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. if tcs is set to an external clock, rpinrx (txck) must be configured to an available rpn/rpin pin. for more informa- tion, see section 10.4 ?peripheral pin select (pps)? . 4. load the timer period value. pr3 (or pr5) will contain the most significant word (msw) of the value while pr2 (or pr4) contains the least significant word (lsw). 5. if interrupts are required, set the interrupt enable bit, t3ie or t5ie; use the priority bits, t3ip<2:0> or t5ip<2:0>, to set the interrupt priority. note that while timer2 or timer4 controls the timer, the interrupt appears as a timer3 or timer5 interrupt. 6. set the ton bit (= 1 ). the timer value, at any point, is stored in the register pair, tmr<3:2> (or tmr<5:4>). tmr3 (tmr5) always contains the most significant word of the count, while tmr2 (tmr4) contains the least significant word. to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer (t2con<3> for timer2 and timer3 or t4con<3> for timer4 and timer5). 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. see section 10.4 ?peripheral pin select (pps)? for more information. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie; use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton (txcon<15> = 1 ) bit. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 14. ?timers? (ds39704). the information in this data sheet supersedes the information in the frm. note: for 32-bit operation, t3con and t5con control bits are ignored. only t2con and t4con control bits are used for setup and control. timer2 and timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the timer3 or timer5 interrupt flags.
pic24fj256gb210 family ds39975a-page 186 ? 2010 microchip technology inc. figure 12-1: timer2/3 and timer4/5 (32-bit) block diagram tmr3 tmr2 set t3if (t5if) equal comparator pr3 pr2 reset lsb msb note 1: the 32-bit timer configuration bit, t32, must be set for 32-bit timer/counter operation. all control bits are respective to the t2con and t4con registers. 2: the timer clock input must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. 3: the adc event trigger is available only on timer 2/3 in 32-bit mode and timer 3 in 16-bit mode. data bus<15:0> tmr3hld read tmr2 (tmr4) (1) write tmr2 (tmr4) (1) 16 16 16 q qd ck tgate 0 1 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs (2) tgate (2) gate t2ck sync adc event trigger (3) sync (t4ck) (pr5) (pr4) (tmr5hld) (tmr5) (tmr4) 1x 01 00
? 2010 microchip technology inc. ds39975a-page 187 pic24fj256gb210 family figure 12-2: timer2 and timer4 (16-bit synchronous) block diagram figure 12-3: timer3 and timer5 (16-bit asynchronous) block diagram ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs (1) 1x 01 tgate (1) 00 gate t2ck sync pr2 (pr4) set t2if (t4if) equal comparator tmr2 (tmr4) reset q q d ck tgate 1 0 (t4ck) sync note 1: the timer clock input must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. ton tckps<1:0> 2 t cy tcs (1) 1x 01 tgate (1) 00 t3ck pr3 (pr5) set t3if (t5if) equal comparator tmr3 (tmr5) reset q q d ck tgate 1 0 adc event trigger (2) (t5ck) prescaler 1, 8, 64, 256 sync note 1: the timer clock input must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. 2: the adc event trigger is available only on timer3.
pic24fj256gb210 family ds39975a-page 188 ? 2010 microchip technology inc. register 12-1: txcon: timer2 and timer4 control register (3) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps1 tckps0 t32 (1) ?tcs (2) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when txcon<3> = 1 : 1 = starts 32-bit timerx/y 0 = stops 32-bit timerx/y when txcon<3> = 0 : 1 = starts 16-bit timerx 0 = stops 16-bit timerx bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit (1) 1 = timerx and timery form a single 32-bit timer 0 = timerx and timery act as two 16-bit timers in 32-bit mode, t3con control bits do not affect 32-bit timer operation. bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timerx clock source select bit (2) 1 = external clock from pin, txck (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: in t4con, the t45 bit is implemented instead of t32 to select 32-bit mode. in 32-bit mode, the t3con or t5con control bits do not affect 32-bit timer operation. 2: if tcs = 1 , rpinrx (txck) must be configured to an available rpn/rpin pin. for more information, see section 10.4 ?peripheral pin select (pps)? . 3: changing the value of txcon while the timer is running (ton = 1 ) causes the timer prescale counter to reset and is not recommended.
? 2010 microchip technology inc. ds39975a-page 189 pic24fj256gb210 family register 12-2: tycon: timer3 and timer5 control register (3) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl (1) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ?tgate (1) tckps1 (1) tckps0 (1) ? ?tcs (1,2) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timery on bit (1) 1 = starts 16-bit timery 0 = stops 16-bit timery bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timery gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timery input clock prescale select bits (1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timery clock source select bit (1,2) 1 = external clock from pin, tyck (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit operation is enabled (t2con<3> or t4con<3> = 1 ), these bits have no effect on timery operation; all timer functions are set through t2con and t4con. 2: if tcs = 1 , rpinrx (txck) must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information. 3: changing the value of tycon while the timer is running (ton = 1 ) causes the timer prescale counter to reset and is not recommended.
pic24fj256gb210 family ds39975a-page 190 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 191 pic24fj256gb210 family 13.0 input capture with dedicated timers devices in the pic24fj256gb210 family comprise nine independent input capture modules. each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. key features of the input capture module include: ? hardware configurable for 32-bit operation in all modes by cascading two adjacent modules ? synchronous and trigger modes of output compare operation, with up to 30 user-selectable sync/trigger sources available ? a 4-level fifo buffer for capturing and holding timer values for several events ? configurable interrupt generation ? up to 6 clock sources available for each module, driving a separate internal 16-bit counter the module is controlled through two registers: icxcon1 (register 13-1) and icxcon2 (register 13-2). a general block diagram of the module is shown in figure 13-1. 13.1 general operating modes 13.1.1 synchronous and trigger modes when the input capture module operates in a free-running mode, the internal 16-bit counter, icxtmr, counts up continuously, wrapping around from ffffh to 0000h on each overflow, with its period synchronized to the selected external clock source. when a capture event occurs, the current 16-bit value of the internal counter is written to the fifo buffer. in synchronous mode, the module begins capturing events on the icx pin as soon as its selected clock source is enabled. whenever an event occurs on the selected sync source, the internal counter is reset. in trigger mode, the module waits for a sync event from another internal module to occur before allowing the internal counter to run. standard, free-running operation is selected by setting the syncsel bits (icxcon2<4:0>) to ? 00000 ? and clearing the ictrig bit (icxcon2<7>). synchronous and trigger modes are selected any time the syncsel bits are set to any value except ? 00000 ?. the ictrig bit selects either synchronous or trigger mode; setting the bit selects trigger mode operation. in both modes, the syncsel bits determine the sync/trigger source. when the syncsel bits are set to ? 00000 ? and ictrig is set, the module operates in software trigger mode. in this case, capture operations are started by manually setting the trigstat bit (icxcon2<6>). figure 13-1: input capture block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 34. ?input capture with dedicated timer? (ds39722). the infor- mation in this data sheet supersedes the information in the frm. note 1: the icx inputs must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. icxbuf 4-level fifo buffer icx pin (1) icm<2:0> set icxif edge detect logic ici1<:0> icov, icbne interrupt logic system bus prescaler counter 1:1/4/16 and clock synchronizer event and clock select ic clock sources sync and ictsel<2:0> syncsel<4:0> trigger 16 16 16 icxtmr increment reset sync and trigger logic trigger sources
pic24fj256gb210 family ds39975a-page 192 ? 2010 microchip technology inc. 13.1.2 cascaded (32-bit) mode by default, each module operates independently with its own 16-bit timer. to increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (for example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) the odd numbered module (icx) provides the least signif- icant 16 bits of the 32-bit register pairs and the even module (icy) provides the most significant 16 bits. wrap-arounds of the icx registers cause an increment of their corresponding icy registers. cascaded operation is configured in hardware by setting the ic32 bits (icxcon2<8>) for both modules. 13.2 capture operations the input capture module can be configured to capture timer values and generate interrupts on rising edges on icx or all transitions on icx. captures can be config- ured to occur on all rising edges or just some (every 4 th or 16 th ). interrupts can be independently configured to generate on each event or a subset of events. to set up the module for capture operations: 1. configure the icx input for one of the available peripheral pin select pins. 2. if synchronous mode is to be used, disable the sync source before proceeding. 3. make sure that any previous data has been removed from the fifo by reading icxbuf until the icbne bit (icxcon1<3>) is cleared. 4. set the syncsel bits (icxcon2<4:0>) to the desired sync/trigger source. 5. set the ictsel bits (icxcon1<12:10>) for the desired clock source. 6. set the ici bits (icxcon1<6:5>) to the desired interrupt frequency 7. select synchronous or trigger mode operation: a) check that the syncsel bits are not set to ? 00000 ?. b) for synchronous mode, clear the ictrig bit (icxcon2<7>). c) for trigger mode, set ictrig, and clear the trigstat bit (icxcon2<6>). 8. set the icm bits (icxcon1<2:0>) to the desired operational mode. 9. enable the selected sync/trigger source. for 32-bit cascaded operations, the setup procedure is slightly different: 1. set the ic32 bits for both modules (icycon2<8>) and (icxcon2<8>), enabling the even numbered module first. this ensures the modules will start functioning in unison. 2. set the ictsel and syncsel bits for both modules to select the same sync/trigger and time base source. set the even module first, then the odd module. both modules must use the same ictsel and syncsel settings. 3. clear the ictrig bit of the even module (icycon2<7>). this forces the module to run in synchronous mode with the odd module, regardless of its trigger setting. 4. use the odd module?s ici bits (icxcon1<6:5>) to set the desired interrupt frequency. 5. use the ictrig bit of the odd module (icxcon2<7>) to configure trigger or synchronous mode operation. 6. use the icm bits of the odd module (icxcon1<2:0>) to set the desired capture mode. the module is ready to capture events when the time base and the sync/trigger source are enabled. when the icbne bit (icxcon1<3>) becomes set, at least one capture value is available in the fifo. read input capture values from the fifo until the icbne clears to ? 0 ?. for 32-bit operation, read both the icxbuf and icybuf for the full 32-bit timer value (icxbuf for the lsw, icybuf for the msw). at least one capture value is available in the fifo buffer when the odd module?s icbne bit (icxcon1<3>) becomes set. continue to read the buffer registers until icbne is cleared (performed automatically by hardware). note: for synchronous mode operation, enable the sync source as the last step. both input capture modules are held in reset until the sync source is enabled.
? 2010 microchip technology inc. ds39975a-page 193 pic24fj256gb210 family register 13-1: icxcon1: input capture x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r-0, hsc r-0, hsc r/w-0 r/w-0 r/w-0 ? ici1 ici0 icov icbne icm2 (1) icm1 (1) icm0 (1) bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture x module stop in idle control bit 1 = input capture module halts in cpu idle mode 0 = input capture module continues to operate in cpu idle mode bit 12-10 ictsel<2:0>: input capture timer select bits 111 = system clock (f osc /2) 110 = reserved 101 = reserved 100 = timer1 011 = timer5 010 = timer4 001 = timer2 000 = timer3 bit 9-7 unimplemented: read as ? 0 ? bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture x overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture x buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits (1) 111 = interrupt mode: input capture functions as an interrupt pin only when the device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable) 110 = unused (module disabled) 101 = prescaler capture mode: capture on every 16 th rising edge 100 = prescaler capture mode: capture on every 4 th rising edge 011 = simple capture mode: capture on every rising edge 010 = simple capture mode: capture on every falling edge 001 = edge detect capture mode: capture on every edge (rising and falling); ici<1:0> bits do not control interrupt generation for this mode 000 = input capture module is turned off note 1: the icx input must also be configured to an available rpn/rpin pin. for more information, see section 10.4 ?peripheral pin select (pps)? .
pic24fj256gb210 family ds39975a-page 194 ? 2010 microchip technology inc. register 13-2: icxcon2: input capture x control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ic32 bit 15 bit 8 r/w-0 r/w-0 hs u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 ic32: cascade two ic modules enable bit (32-bit operation) 1 = icx and icy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = icx functions independently as a 16-bit module bit 7 ictrig: icx sync/trigger select bit 1 = trigger icx from the source designated by the syncselx bits 0 = synchronize icx with the source designated by the syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running (set in hardware, can be set in software) 0 = timer source has not been triggered and is being held clear bit 5 unimplemented: read as ? 0 ? bit 4-0 syncsel<4:0>: synchronization/trigger source selection bits 11111 = reserved 11110 = input capture 9 (2) 11101 = input capture 6 (2) 11100 = ctmu (1) 11011 = a/d (1) 11010 = comparator 3 (1) 11001 = comparator 2 (1) 11000 = comparator 1 (1) 10111 = input capture 4 (2) 10110 = input capture 3 (2) 10101 = input capture 2 (2) 10100 = input capture 1 (2) 10011 = input capture 8 (2) 10010 = input capture 7 (2) 1000x = reserved 01111 = timer5 01110 = timer4 01101 = timer3 01100 = timer2 01011 = timer1 01010 = input capture 5 (2) 01001 = output compare 9 . . . 00010 = output compare 2 00001 = output compare 1 00000 = not synchronized to any other module note 1: use these inputs as trigger sources only and never as sync sources. 2: never use an ic module as its own trigger source by selecting this mode.
? 2010 microchip technology inc. ds39975a-page 195 pic24fj256gb210 family 14.0 output compare with dedicated timers devices in the pic24fj256gb210 family feature all of the 9 independent output compare modules. each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications. key features of the output compare module include: ? hardware configurable for 32-bit operation in all modes by cascading two adjacent modules ? synchronous and trigger modes of output compare operation, with up to 31 user-selectable trigger/sync sources available ? two separate period registers (a main register, ocxr, and a secondary register, ocxrs) for greater flexibility in generating pulses of varying widths ? configurable for single pulse or continuous pulse generation on an output event, or continuous pwm waveform generation ? up to 6 clock sources available for each module, driving a separate internal 16-bit counter 14.1 general operating modes 14.1.1 synchronous and trigger modes when the output compare module operates in a free-running mode, the internal 16-bit counter, ocxtmr, runs counts up continuously, wrapping around from 0xffff to 0x0000 on each overflow, with its period synchronized to the selected external clock source. compare or pwm events are generated each time a match between the internal counter and one of the period registers occurs. in synchronous mode, the module begins performing its compare or pwm operation as soon as its selected clock source is enabled. whenever an event occurs on the selected sync source, the module?s internal counter is reset. in trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. free-running mode is selected by default or any time that the syncsel bits (ocxcon2<4:0>) are set to ? 00000 ?. synchronous or trigger modes are selected any time the syncsel bits are set to any value except ? 00000 ?. the octrig bit (ocxcon2<7>) selects either synchronous or trigger mode; setting the bit selects trigger mode operation. in both modes, the syncsel bits determine the sync/trigger source. 14.1.2 cascaded (32-bit) mode by default, each module operates independently with its own set of 16-bit timer and duty cycle registers. to increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (for example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) the odd numbered module (ocx) provides the least significant 16 bits of the 32-bit register pairs and the even module (ocy) provides the most significant 16 bits. wrap-arounds of the ocx registers cause an increment of their corresponding ocy registers. cascaded operation is configured in hardware by set- ting the oc32 bit (ocxcon2<8>) for both modules. for more details on cascading, refer to the ? pic24f family reference manual ?, section 35. ?output compare with dedicated timer? . note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual?, section 35. ?output compare with dedicated timer? (ds39723). the infor- mation in this data sheet supersedes the information in the frm.
pic24fj256gb210 family ds39975a-page 196 ? 2010 microchip technology inc. figure 14-1: output compare block diagram (16-bit mode) 14.2 compare operations in compare mode (figure 14-1), the output compare module can be configured for single-shot or continuous pulse generation. it can also repeatedly toggle an output pin on each timer event. to set up the module for compare operations: 1. configure the ocx output for one of the available peripheral pin select pins. 2. calculate the required values for the ocxr and (for double compare modes) ocxrs duty cycle registers: a) determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 3. write the rising edge value to ocxr and the falling edge value to ocxrs. 4. set the timer period register, pry, to a value equal to or greater than the value in ocxrs. 5. set the ocm<2:0> bits for the appropriate compare operation (= 0xx ). 6. for trigger mode operations, set octrig to enable trigger mode. set or clear trigmode to configure trigger operation and trigstat to select a hardware or software trigger. for synchronous mode, clear octrig. 7. set the syncsel<4:0> bits to configure the trigger or synchronization source. if free-running timer operation is required, set the syncsel bits to ? 00000 ? (no sync/trigger source). 8. select the time base source with the octsel<2:0> bits. if necessary, set the ton bits for the selected timer, which enables the compare time base to count. synchronous mode operation starts as soon as the time base is enabled; trigger mode operation starts after a trigger source event occurs. ocxr and comparator ocxtmr ocxcon1 ocxcon2 oc output and ocx interrupt ocx pin (1) ocxrs comparator fault logic match event match event trigger and sync logic clock select increment reset oc clock sources trigger and sync sources reset match event ocfa/ocfb (2) octselx syncselx trigstat trigmode octrig ocmx ocinv octris fltout flttrien fltmd enflt<2:0> ocflt<2:0> note 1: the ocx outputs must be assigned to an available rpn pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. 2: the ocfa/ocfb fault inputs must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. dcb<1:0> dcb<1:0>
? 2010 microchip technology inc. ds39975a-page 197 pic24fj256gb210 family for 32-bit cascaded operation, these steps are also necessary: 1. set the oc32 bits for both registers (ocycon2<8> and ocxcon2<8>). enable the even numbered module first to ensure the modules will start functioning in unison. 2. clear the octrig bit of the even module (ocycon2) so the module will run in synchronous mode. 3. configure the desired output and fault settings for ocy. 4. force the output pin for ocx to the output state by clearing the octris bit. 5. if trigger mode operation is required, configure the trigger options in ocx by using the octrig (ocxcon2<7>), trig mode (ocxcon1<3>) and syncsel (ocxcon2<4:0>) bits. 6. configure the desired compare or pwm mode of operation (ocm<2:0>) for ocy first, then for ocx. depending on the output mode selected, the module holds the ocx pin in its default state and forces a tran- sition to the opposite state when ocxr matches the timer. in double compare modes, ocx is forced back to its default state when a match with ocxrs occurs. the ocxif interrupt flag is set after an ocxr match in single compare modes and after each ocxrs match in double compare modes. single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the ocxcon1 register. continuous pulse events continue indefinitely until terminated. 14.3 pulse-width modulation (pwm) mode in pwm mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. all pwm operations are double-buffered (buffer registers are internal to the module and are not mapped into sfr space). to configure the output compare module for pwm operation: 1. configure the ocx output for one of the available peripheral pin select pins. 2. calculate the desired duty cycles and load them into the ocxr register. 3. calculate the desired period and load it into the ocxrs register. 4. select the current ocx as the synchronization source by writing 0x1f to the syncsel<4:0> bits (ocxcon2<4:0>) and ? 0 ? to the octrig bit (ocxcon2<7>). 5. select a clock source by writing to the octsel<2:0> bits (ocxcon<12:10>). 6. enable interrupts, if required, for the timer and output compare modules. the output compare interrupt is required for pwm fault pin utilization. 7. select the desired pwm mode in the ocm<2:0> bits (ocxcon1<2:0>). 8. appropriate fault inputs may be enabled by using the enflt<2:0> bits as described in register 14-1. 9. if a timer is selected as a clock source, set the selected timer prescale value. the selected timer?s prescaler output is used as the clock input for the ocx timer, and not the selected timer output. note: this peripheral contains input and output functions that may need to be configured by the peripheral pin select. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 198 ? 2010 microchip technology inc. figure 14-2: output compare block diagram (double-buffered, 16-bit pwm mode) 14.3.1 pwm period the pwm period is specified by writing to pry, the timer period register. the pwm period can be calculated using equation 14-1. equation 14-1: calculating the pwm period (1) ocxr and comparator ocxtmr ocxcon1 ocxcon2 oc output and ocx interrupt ocx pin (1) ocxrs buffer comparator fault logic match match trigger and sync logic clock select increment reset oc clock sources trigger and sync sources reset match event ocfa/ocfb (2) octselx syncselx trigstat trigmode octrig ocmx ocinv octris fltout flttrien fltmd enflt<2:0> ocflt<2:0> ocxrs event event rollover rollover/reset rollover/reset note 1: the ocx outputs must be assigned to an available rpn pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. 2: the ocfa/ocfb fault inputs must be assigned to an available rpn/rpin pin before use. see section 10.4 ?peripheral pin select (pps)? for more information. ocxr and dcb<1:0> dcb<1:0> dcb<1:0> buffers note 1: based on t cy = t osc * 2; doze mode and pll are disabled. pwm period = [(pry) + 1 ? t cy ? (timer prescale value) where: pwm frequency = 1/[pwm period] note: a pry value of n will produce a pwm period of n + 1 time base count cycles. for example, a value of 7 written into the pry register will yield a period consisting of 8 time base cycles.
? 2010 microchip technology inc. ds39975a-page 199 pic24fj256gb210 family 14.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ocxrs and ocxr registers. the ocxrs and ocxr registers can be written to at any time, but the duty cycle value is not latched until a match between pry and tmry occurs (i.e., the period is complete). this provides a double buffer for the pwm duty cycle and is essential for glitchless pwm operation. some important boundary parameters of the pwm duty cycle include: ? if ocxr, ocxrs, and pry are all loaded with 0000h, the ocx pin will remain low (0% duty cycle). ? if ocxrs is greater than pry, the pin will remain high (100% duty cycle). see example 14-1 for pwm mode timing details. table 14-1 and table 14-2 show example pwm frequencies and resolutions for a device operating at 4 mips and 10 mips, respectively. equation 14-2: calculation for maximum pwm resolution (1) example 14-1: pwm period and duty cycle calculations (1) note 1: based on f cy = f osc /2; doze mode and pll are disabled. maximum pwm resolution (bits) = log 10 log 10 (2) fpwm ? (timer prescale value) bits f cy () 1. find the timer period register value for a desired pwm frequency of 52.08 khz, where f osc = 8 mhz with pll (32 mhz device clock rate) and a timer2 prescaler setting of 1:1. t cy = 2 * t osc = 62.5 ns pwm period = 1/pwm frequency = 1/52.08 khz = 19.2 ms pwm period = (pr2 + 1) ? t cy ? (timer2 prescale value) 19.2 ms = pr2 + 1) ? 62.5 ns ? 1 pr2 = 306 2. find the maximum resolution of the duty cycle that can be used with a 52.08 khz frequency and a 32 mhz device clock rate: pwm resolution = log 10 (f cy /f pwm )/log 10 2) bits = (log 10 (16 mhz/52.08 khz)/log 10 2) bits = 8.3 bits note 1: based on t cy = 2 * t osc ; doze mode and pll are disabled. table 14-1: example pwm frequencies and resolutions at 4 mips (f cy = 4 mhz) (1) pwm frequency 7.6 hz 61 hz 122 hz 977 hz 3.9 khz 31.3 khz 125 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on f cy = f osc /2; doze mode and pll are disabled. table 14-2: example pwm frequencies and resolutions at 16 mips (f cy = 16 mhz) (1) pwm frequency 30.5 hz 244 hz 488 hz 3.9 khz 15.6 khz 125 khz 500 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on f cy = f osc /2; doze mode and pll are disabled.
pic24fj256gb210 family ds39975a-page 200 ? 2010 microchip technology inc. register 14-1: ocxcon1: output compare x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 (2) enflt1 (2) bit 15 bit 8 r/w-0 r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 enflt0 (2) ocflt2 (2) ocflt1 (2) ocflt0 (2) trigmode ocm2 (1) ocm1 (1) ocm0 (1) bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare x in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-10 octsel<2:0>: output compare x timer select bits 111 = peripheral clock (f cy ) 110 = reserved 101 = reserved 100 = timer1 clock (only the synchronous clock is supported) 011 = timer5 clock 010 = timer4 clock 001 = timer3 clock 000 = timer2 clock bit 9 enflt2: fault input 2 enable bit (2) 1 = fault 2 (comparator 1/2/3 out) is enabled (3) 0 = fault 2 is disabled bit 8 enflt1: fault input 1 enable bit (2) 1 = fault 1 (ocfb pin) is enabled (4) 0 = fault 1 is disabled bit 7 enflt0: fault input 0 enable bit (2) 1 = fault 0 (ocfa pin) is enabled (4) 0 = fault 0 is disabled bit 6 ocflt2: pwm fault 2 (comparator 1/2/3) condition status bit (2,3) 1 = pwm fault 2 has occurred 0 = no pwm fault 2 has occurred bit 5 ocflt1: pwm fault 1 (ocfb pin) condition status bit (2,4) 1 = pwm fault 1 has occurred 0 = no pwm fault 1 has occurred bit 4 ocflt0: pwm fault 0 (ocfa pin) condition status bit (2,4) 1 = pwm fault 0 has occurred 0 = no pwm fault 0 has occurred note 1: the ocx output must also be configured to an available rpn pin. for more information, see section 10.4 ?peripheral pin select (pps)? . 2: the fault input enable and fault status bits are valid when ocm<2:0> = 111 or 110 . 3: the comparator 1 output controls the oc1-oc3 chan nels; comparator 2 output controls the oc4-oc6 channels. comparator 3 output controls the oc7-oc9 channels. 4: the ocfa/ocfb fault input must also be configured to an available rpn/rpin pin. for more information, see section 10.4 ?peripheral pin select (pps)? .
? 2010 microchip technology inc. ds39975a-page 201 pic24fj256gb210 family bit 3 trigmode: trigger status mode select bit 1 = trigstat (ocxcon2<6>) is cleared when ocxrs = ocxtmr or in software 0 = trigstat is only cleared by software bit 2-0 ocm<2:0>: output compare x mode select bits (1) 111 = center-aligned pwm mode on ocx (2) 110 = edge-aligned pwm mode on ocx (2) 101 = double compare continuous pulse mode: initialize the ocx pin low, the toggle ocx state is continuously on alternate matches of ocxr and ocxrs 100 = double compare single-shot mode: initialize the ocx pin low, toggle the ocx state on matches of ocxr and ocxrs for one cycle 011 = single compare continuous pulse mode: compare events continuously toggle the ocx pin 010 = single compare single-shot mode: initialize ocx pin high, compare event forces the ocx pin low 001 = single compare single-shot mode: initialize ocx pin low, compare event forces the ocx pin high 000 = output compare channel is disabled register 14-1: ocxcon1: output compare x control register 1 (continued) note 1: the ocx output must also be configured to an available rpn pin. for more information, see section 10.4 ?peripheral pin select (pps)? . 2: the fault input enable and fault status bits are valid when ocm<2:0> = 111 or 110 . 3: the comparator 1 output controls the oc1-oc3 chan nels; comparator 2 output controls the oc4-oc6 channels. comparator 3 output controls the oc7-oc9 channels. 4: the ocfa/ocfb fault input must also be configured to an available rpn/rpin pin. for more information, see section 10.4 ?peripheral pin select (pps)? .
pic24fj256gb210 family ds39975a-page 202 ? 2010 microchip technology inc. register 14-2: ocxcon2: output compare x control register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 fltmd fltout flttrien ocinv ? dcb1 (3) dcb0 (3) oc32 bit 15 bit 8 r/w-0 r/w-0 hs r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 fltmd: fault mode select bit 1 = fault mode is maintained until the fault source is removed and the corresponding ocflt0 bit is cleared in software 0 = fault mode is maintained until the fault source is removed and a new pwm period starts bit 14 fltout: fault out bit 1 = pwm output is driven high on a fault 0 = pwm output is driven low on a fault bit 13 flttrien: fault output state select bit 1 = pin is forced to an output on a fault condition 0 = pin i/o condition is unaffected by a fault bit 12 ocinv: ocmp invert bit 1 = ocx output is inverted 0 = ocx output is not inverted bit 11 unimplemented: read as ? 0 ? bit 10-9 dcb<11:0>: pwm duty cycle least significant bits (3) 11 = delay ocx falling edge by ? of the instruction cycle 10 = delay ocx falling edge by ? of the instruction cycle 01 = delay ocx falling edge by ? of the instruction cycle 00 = ocx falling edge occurs at the start of the instruction cycle bit 8 oc32: cascade two oc modules enable bit (32-bit operation) 1 = cascade module operation is enabled 0 = cascade module operation is disabled bit 7 octrig: ocx trigger/sync select bit 1 = trigger ocx from the source designated by the syncselx bits 0 = synchronize ocx with the source designated by the syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running 0 = timer source has not been triggered and is being held clear bit 5 octris: ocx output pin direction select bit 1 = ocx pin is tri-stated 0 = output compare peripheral x is connected to an ocx pin note 1: never use an oc module as its own trigger source, either by selecting this mode or another equivalent syncsel setting. 2: use these inputs as trigger sources only and never as sync sources. 3: the dcb<1:0> bits are double-buffered in the pwm modes only (ocm<2:0> (ocxcon1<2:0>) = 111 , 110 ).
? 2010 microchip technology inc. ds39975a-page 203 pic24fj256gb210 family bit 4-0 syncsel<4:0>: trigger/synchronization source selection bits 11111 = this oc module (1) 11110 = input capture 9 (2) 11101 = input capture 6 (2) 11100 = ctmu (2) 11011 = a/d (2) 11010 = comparator 3 (2) 11001 = comparator 2 (2) 11000 = comparator 1 (2) 10111 = input capture 4 (2) 10110 = input capture 3 (2) 10101 = input capture 2 (2) 10100 = input capture 1 (2) 10011 = input capture 8 (2) 10010 = input capture 7 (2) 1000x = reserved 01111 = timer5 01110 = timer4 01101 = timer3 01100 = timer2 01011 = timer1 01010 = input capture 5 (2) 01001 = output compare 9 (1) 01000 = output compare 8 (1) 00111 = output compare 7 (1) 00110 = output compare 6 (1) 00101 = output compare 5 (1) 00100 = output compare 4 (1) 00011 = output compare 3 (1) 00010 = output compare 2 (1) 00001 = output compare 1 (1) 00000 = not synchronized to any other module register 14-2: ocxcon2: output compare x control register 2 (continued) note 1: never use an oc module as its own trigger source, either by selecting this mode or another equivalent syncsel setting. 2: use these inputs as trigger sources only and never as sync sources. 3: the dcb<1:0> bits are double-buffered in the pwm modes only (ocm<2:0> (ocxcon1<2:0>) = 111 , 110 ).
pic24fj256gb210 family ds39975a-page 204 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 205 pic24fj256gb210 family 15.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the spi module is compatible with the spi and siop motorola ? interfaces. all devices of the pic24fj256gb210 family include three spi modules. the module supports operation in two buffer modes. in standard mode, data is shifted through a single serial buffer. in enhanced buffer mode, data is shifted through an 8-level fifo buffer. the module also supports a basic framed spi protocol while operating in either master or slave mode. a total of four framed spi configurations are supported. the spi serial interface consists of four pins: ? sdix: serial data input ? sdox: serial data output ? sckx: shift clock input or output ? ssx : active-low slave select or frame synchronization i/o pulse the spi module can be configured to operate using 2, 3 or 4 pins. in the 3-pin mode, ssx is not used. in the 2-pin mode, both sdox and ssx are not used. block diagrams of the module in standard and enhanced modes are shown in figure 15-1 and figure 15-2. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 23. ?serial peripheral interface (spi)? (ds39699). the information in this data sheet supersedes the information in the frm. note: do not perform read-modify-write opera- tions (such as bit-oriented instructions) on the spixbuf register in either standard or enhanced buffer mode. note: in this section, the spi modules are referred to together as spix or separately as spi1, spi2 or spi3. special function registers will follow a similar notation. for example, spixcon1 and spixcon2 refer to the control registers for any of the 3 spi modules.
pic24fj256gb210 family ds39975a-page 206 ? 2010 microchip technology inc. to set up the spi module for the standard master mode of operation: 1. if using interrupts: a) clear the spixif bit in the respective ifs register. b) set the spixie bit in the respective iec register. c) write the spixip bits in the respective ipc register to set the interrupt priority. 2. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 1 . 3. clear the spirov bit (spixstat<6>). 4. enable spi operation by setting the spien bit (spixstat<15>). 5. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. to set up the spi module for the standard slave mode of operation: 1. clear the spixbuf register. 2. if using interrupts: a) clear the spixif bit in the respective ifs register. b) set the spixie bit in the respective iec register. c) write the spixip bits in the respective ipc register to set the interrupt priority. 3. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit (spixcon1<8>) is set, then the ssen bit (spixcon1<7>) must be set to enable the ssx pin. 6. clear the spirov bit (spixstat<6>). 7. enable spi operation by setting the spien bit (spixstat<15>). figure 15-1: spix mo dule block diagram (standard mode) internal data bus sdix sdox ssx /fsyncx sckx spixsr bit 0 shift control edge select primary 1:1/4/16/64 enable prescaler sync clock control spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock secondary prescaler 1:1 to 1:8 f cy
? 2010 microchip technology inc. ds39975a-page 207 pic24fj256gb210 family to set up the spi module for the enhanced buffer master mode of operation: 1. if using interrupts: a) clear the spixif bit in the respective ifs register. b) set the spixie bit in the respective iec register. c) write the spixip bits in the respective ipc register. 2. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 1 . 3. clear the spirov bit (spixstat<6>). 4. select enhanced buffer mode by setting the spiben bit (spixcon2<0>). 5. enable spi operation by setting the spien bit (spixstat<15>). 6. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. to set up the spi module for the enhanced buffer slave mode of operation: 1. clear the spixbuf register. 2. if using interrupts: a) clear the spixif bit in the respective ifs register. b) set the spixie bit in the respective iec register. c) write the spixip bits in the respective ipc register to set the interrupt priority. 3. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then the ssen bit must be set, thus enabling the ssx pin. 6. clear the spirov bit (spixstat<6>). 7. select enhanced buffer mode by setting the spiben bit (spixcon2<0>). 8. enable spi operation by setting the spien bit (spixstat<15>). figure 15-2: spix mo dule block diagram (enhanced mode) internal data bus sdix sdox ss x /fsyncx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler secondary prescaler 1:1 to 1:8 sync clock control spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock 8-level fifo transmit buffer 8-level fifo receive buffer
pic24fj256gb210 family ds39975a-page 208 ? 2010 microchip technology inc. register 15-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc spien (1) ? spisidl ? ? spibec2 spibec1 spibec0 bit 15 bit 8 r-0, hsc r/c-0, hs r-0, hsc r/w-0 r/w-0 r/w-0 r-0, hsc r-0, hsc srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hsc = hardware settable/clearable bit bit 15 spien: spix enable bit (1) 1 = enables the module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables themodule bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 spibec<2:0>: spix buffer element count bits (valid in enhanced buffer mode) master mode : number of spi transfers pending. slave mode : number of spi transfers unread. bit 7 srmpt: shift register (spixsr) empty bit (valid in enhanced buffer mode) 1 = spix shift register is empty and ready to send or receive 0 = spix shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded (the user software has not read the previous data in the spixbuf register.) 0 = no overflow has occurred bit 5 srxmpt: receive fifo empty bit (valid in enhanced buffer mode) 1 = receive fifo is empty 0 = receive fifo is not empty bit 4-2 sisel<2:0>: spix buffer interrupt mode bits (valid in enhanced buffer mode) 111 = interrupt when the spix transmit buffer is full (spitbf bit is set) 110 = interrupt when the last bit is shifted into spixsr; as a result, the tx fifo is empty 101 = interrupt when the last bit is shifted out of spixsr; now the transmit is complete 100 = interrupt when one data is shifted into the spixsr; as a result, the tx fifo has one open spot 011 = interrupt when the spix receive buffer is full (spirbf bit set) 010 = interrupt when the spix receive buffer is 3/4 or more full 001 = interrupt when data is available in the receive buffer (srmpt bit is set) 000 = interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (srxmpt bit set) note 1: if spien = 1 , these functions must be assigned to available rpn/rpin pins before use. see section 10.4 ?peripheral pin select (pps)? for more information.
? 2010 microchip technology inc. ds39975a-page 209 pic24fj256gb210 family bit 1 spitbf: spix transmit buffer full status bit 1 = transmit has not yet started, spixtxb is full 0 = transmit has started, spixtxb is empty in standard buffer mode: automatically set in hardware when the cpu writes to the spixbuf location, loading spixtxb. automatically cleared in hardware when the spix module transfers data from spixtxb to spixsr. in enhanced buffer mode: automatically set in hardware when the cpu writes to the spixbuf location, loading the last available buffer location. automatically cleared in hardware when a buffer location is available for a cpu write. bit 0 spirbf: spix receive buffer full status bit 1 = receive is complete, spixrxb is full 0 = receive is not complete, spixrxb is empty in standard buffer mode: automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when the core reads the spixbuf location, reading spixrxb. in enhanced buffer mode: automatically set in hardware when spix transfers data from the spixsr to the buffer, filling the last unread buffer location. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. register 15-1: spixstat: spix status and control register (continued) note 1: if spien = 1 , these functions must be assigned to available rpn/rpin pins before use. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 210 ? 2010 microchip technology inc. register 15-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck (1) dissdo (2) mode16 smp cke (3) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen (4) ckp msten spre2 spre1 spre0 ppre1 ppre0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) (1) 1 = internal spi clock is disabled; pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit (2) 1 = sdox pin is not used by the module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data is sampled at the end of data output time 0 = input data is sampled at the middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit (3) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable (slave mode) bit (4) 1 =ssx pin is used for slave mode 0 =ssx pin is not used by the module; pin is controlled by the port function bit 6 ckp: clock polarity select bit 1 = idle state for the clock is a high level; active state is a low level 0 = idle state for the clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode note 1: if dissck = 0 , sckx must be configured to an available rpn pin. see section 10.4 ?peripheral pin select (pps)? for more information. 2: if dissdo = 0 , sdox must be configured to an available rpn pin. see section 10.4 ?peripheral pin select (pps)? for more information. 3: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 4: if ssen = 1 , ssx must be configured to an available rpn/prin pin. see section 10.4 ?peripheral pin select (pps)? for more information.
? 2010 microchip technology inc. ds39975a-page 211 pic24fj256gb210 family bit 4-2 spre<2:0>: secondary prescale bits (master mode) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 . . . 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 15-2: spi x con1: spix control register 1 (continued) note 1: if dissck = 0 , sckx must be configured to an available rpn pin. see section 10.4 ?peripheral pin select (pps)? for more information. 2: if dissdo = 0 , sdox must be configured to an available rpn pin. see section 10.4 ?peripheral pin select (pps)? for more information. 3: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 4: if ssen = 1 , ssx must be configured to an available rpn/prin pin. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 212 ? 2010 microchip technology inc. register 15-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd spifpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? spife spiben bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support is enabled 0 = framed spix support is disabled bit 14 spifsd: frame sync pulse direction control on ssx pin bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 spifpol: frame sync pulse polarity bit (frame mode only) 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 spife: frame sync pulse edge select bit 1 = frame sync pulse coincides with the first bit clock 0 = frame sync pulse precedes the first bit clock bit 0 spiben: enhanced buffer enable bit 1 = enhanced buffer is enabled 0 = enhanced buffer is disabled (legacy mode)
? 2010 microchip technology inc. ds39975a-page 213 pic24fj256gb210 family figure 15-3: spi master/slave connection (standard mode) figure 15-4: spi master/slave connection (enhanced buffer modes) serial receive buffer (spixrxb) (2) shift register (spixsr) (2) lsb msb sdix sdox processor 2 (spi slave) sckx ssx (1) serial transmit buffer (spixtxb) (2) serial receive buffer (spixrxb) shift register (spixsr) msb lsb sdox sdix processor 1 (spi master) serial clock ssen (spixcon1<7>) = 1 and msten (spixcon1<5>) = 0 note 1: using the ssx pin in slave mode of operation is optional. 2: user must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. sckx serial transmit buffer (spixtxb) msten (spixcon1<5>) = 1 ) spix buffer (spixbuf) (2) spix buffer (spixbuf) (2) shift register (spixsr) lsb msb sdix sdox processor 2 (spi enhanced buffer slave) sckx ssx (1) shift register (spixsr) msb lsb sdox sdix processor 1 (spi enhanced buffer master) serial clock ssen (spixcon1<7>) = 1 , note 1: using the ssx pin in slave mode of operation is optional. 2: user must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. ssx sckx 8-level fifo buffer msten (spixcon1<5>) = 1 and spix buffer (spixbuf) (2) 8-level fifo buffer spix buffer (spixbuf) (2) spiben (spixcon2<0>) = 1 msten (spixcon1<5>) = 0 and spiben (spixcon2<0>) = 1
pic24fj256gb210 family ds39975a-page 214 ? 2010 microchip technology inc. figure 15-5: spi master, fram e master connection diagram figure 15-6: spi master, fr ame slave connection diagram figure 15-7: spi slave, fram e master connection diagram figure 15-8: spi slave, fram e slave connection diagram sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx (spi master, frame master) sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx spi master, frame slave) sdox sdix pic24f serial clock ssx sckx frame sync. pulse sdix sdox processor 2 ssx sckx (spi slave, frame master) sdox sdix pic24f serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx (spi slave, frame slave)
? 2010 microchip technology inc. ds39975a-page 215 pic24fj256gb210 family equation 15-1: relationship between device and spi clock speed (1) note 1: based on f cy = f osc /2; doze mode and pll are disabled. fsck = f cy primary prescaler x secondary prescaler table 15-1: sample sckx frequencies (1,2) f cy = 16 mhz secondary prescaler settings 1:1 2:1 4:1 6:1 8:1 primary prescaler settings 1:1 invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 f cy = 5 mhz primary prescaler settings 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:17839201310 note 1: based on f cy = f osc /2; doze mode and pll are disabled. 2: sckx frequencies shown in khz.
pic24fj256gb210 family ds39975a-page 216 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 217 pic24fj256gb210 family 16.0 inter-integrated circuit? (i 2 c?) the inter-integrated circuit? (i 2 c?) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, display drivers, a/d converters, etc. the i 2 c module supports these features: ? independent master and slave logic ? 7-bit and 10-bit device addresses ? general call address, as defined in the i 2 c protocol ? clock stretching to provide delays for the processor to respond to a slave data request ? both 100 khz and 400 khz bus specifications ? configurable address masking ? multi-master modes to prevent loss of messages in arbitration ? bus repeater mode, allowing the acceptance of all messages as a slave regardless of the address ? automatic scl a block diagram of the module is shown in figure 16-1. 16.1 communicating as a master in a single master environment the details of sending a message in master mode depends on the communications protocol for the device being communicated with. typically, the sequence of events is as follows: 1. assert a start condition on sdax and sclx. 2. send the i 2 c device address byte to the slave with a write indication. 3. wait for and verify an acknowledge from the slave. 4. send the first data byte (sometimes known as the command) to the slave. 5. wait for and verify an acknowledge from the slave. 6. send the serial memory address low byte to the slave. 7. repeat steps 4 and 5 until all data bytes are sent. 8. assert a repeated start condition on sdax and sclx. 9. send the device address byte to the slave with a read indication. 10. wait for and verify an acknowledge from the slave. 11. enable master reception to receive serial memory data. 12. generate an ack or nack condition at the end of a received byte of data. 13. generate a stop condition on sdax and sclx. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 24. ?inter-integrated circuit? (i 2 c?)? (ds39702). the information in this data sheet supersedes the information in the frm.
pic24fj256gb210 family ds39975a-page 218 ? 2010 microchip technology inc. figure 16-1: i 2 c? block diagram i2cxrcv internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk
? 2010 microchip technology inc. ds39975a-page 219 pic24fj256gb210 family 16.2 setting baud rate when operating as a bus master to compute the baud rate generator reload value, use equation 16-1. equation 16-1: computing baud rate reload value (1,2) 16.3 slave address masking the i2cxmsk register (register 16-3) designates address bit positions as ?don?t care? for both 7-bit and 10-bit addressing modes. setting a particular bit loca- tion (= 1 ) in the i2cxmsk register causes the slave module to respond whether the corresponding address bit value is a ? 0 ? or a ? 1 ?. for example, when i2cxmsk is set to ? 00100000 ?, the slave module will detect both addresses, ? 0000000 ? and ? 0100000 ?. to enable address masking, the intelligent peripheral management interface (ipmi) must be disabled by clearing the ipmien bit (i2cxcon<11>). table 16-2: i 2 c? reserved addresses (1) note 1: based on f cy = f osc /2; doze mode and pll are disabled. 2: these clock rate values are for guidance only. the actual clock rate can be affected by various system level parameters. the actual clock rate should be measured in its intended application. fscl = f cy i2cxbrg + 1 + f cy 10,000,000 i2cxbrg = f cy 10,000,000 f cy fscl ?? 1 or: ( ) note: as a result of changes in the i 2 c? proto- col, the addresses in table 16-2 are reserved and will not be acknowledged in slave mode. this includes any address mask settings that include any of these addresses. table 16-1: i 2 c? clock rates(1,2) required system f scl f cy i2cxbrg value actual f scl (decimal) (hexadecimal) 100 khz 16 mhz 157 9d 100 khz 100 khz 8 mhz 78 4e 100 khz 100 khz 4 mhz 39 27 99 khz 400 khz 16 mhz 37 25 404 khz 400 khz 8 mhz 18 12 404 khz 400 khz 4 mhz 9 9 385 khz 400 khz 2 mhz 4 4 385 khz 1 mhz 16 mhz 13 d 1.026 mhz 1mhz 8mhz 6 6 1.026mhz 1mhz 4mhz 3 3 0.909mhz note 1: based on f cy = f osc /2; doze mode and pll are disabled. 2: these clock rate values are for guidance only. the actual clock rate can be affected by various system level parameters. the actual clock rate should be measured in its intended application. slave address r/w bit description 0000 000 0 general call address (2) 0000 000 1 start byte 0000 001 x cbus address 0000 01x x reserved 0000 1xx x hs mode master code 1111 0xx x 10-bit slave upper byte (3) 1111 1xx x reserved note 1: the address bits listed here will never cause an address match, independent of address mask settings. 2: the address will be acknowledged only if gcen = 1 . 3: a match on this address can only occur on the upper byte in 10-bit addressing mode.
pic24fj256gb210 family ds39975a-page 220 ? 2010 microchip technology inc. register 16-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module; all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinues module operation when device enters an idle mode 0 = continues module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software may write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware is clear at the beginning of slave transmission. hardware is clear at the end of slave reception. if stren = 0 : bit is r/s (i.e., software may only write ? 1 ? to release clock). hardware is clear at the beginning of slave transmission. bit 11 ipmien: intelligent platform management interface (ipmi) enable bit 1 = ipmi support mode is enabled; all addresses are acknowledged 0 = ipmi mode is disabled bit 10 a10m: 10-bit slave addressing bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with smbus specifications 0 = disables the smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with the sclrel bit. 1 = enables software or receive clock stretching 0 = disables software or receive clock stretching
? 2010 microchip technology inc. ds39975a-page 221 pic24fj256gb210 family bit 5 ackdt: acknowledge data bit (when operating as i 2 c master. applicable during master receive.) value that will be transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master; applicable during master receive) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits the ackdt data bit. hardware is clear at the end of the master acknowledge sequence. 0 = acknowledge sequence is not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware is clear at the end of the eighth bit of the master receive data byte. 0 = receive sequence is not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on the sdax and sclx pins. hardware is clear at the end of the master stop sequence. 0 = stop condition is not in progress bit 1 rsen: repeated start condition enabled bit (when operating as i 2 c master) 1 = initiates repeated start condition on the sdax and sclx pins. hardware is clear at the end of the master repeated start sequence 0 = repeated start condition is not in progress bit 0 sen: start condition enabled bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins. hardware is clear at end of the master start sequence. 0 = start condition is not in progress register 16-1: i2cxcon: i2cx control register (continued)
pic24fj256gb210 family ds39975a-page 222 ? 2010 microchip technology inc. register 16-2: i2cxstat: i2cx status register r-0, hsc r-0, hsc u-0 u-0 u-0 r/c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d/a psr/w rbf tbf bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hsc = hardware settable/clearable bit bit 15 ackstat: acknowledge status bit 1 = nack was detected last 0 = ack was detected last hardware is set or clear at the end of acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c? master. applicable to master transmit operation.) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware is set at the beginning of master transmission; hardware is clear at the end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware is set at the detection of a bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware is set when the address matches the general call address; hardware is clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware is set at the match of the 2 nd byte of the matched 10-bit address; hardware is clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write to the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware is set at an occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware is set at an attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d/a : data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was a device address hardware is clear at the device address match. hardware is set after a transmission finishes or by reception of a slave byte.
? 2010 microchip technology inc. ds39975a-page 223 pic24fj256gb210 family bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware is set or clear when start, repeated start or stop is detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware is set or clear when start, repeated start or stop is detected. bit 2 r/w : read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from the slave 0 = write ? indicates data transfer is input to the slave hardware is set or clear after the reception of an i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive is complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware is set when i2cxrcv is written with the received byte; hardware is clear when the software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit is in progress, i2cxtrn is full 0 = transmit is complete, i2cxtrn is empty hardware is set when software writes to i2cxtrn; hardware is clear at the completion of data transmission. register 16-2: i2cxstat: i2cx status register (continued)
pic24fj256gb210 family ds39975a-page 224 ? 2010 microchip technology inc. register 16-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amsk<9:0>: mask for address bit x select bits 1 = enable masking for bit x of the incoming message address; bit match is not required in this position 0 = disable masking for bit x; bit match is required in this position
? 2010 microchip technology inc. ds39975a-page 225 pic24fj256gb210 family 17.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the pic24f device family. the uart is a full-duplex, asynchronous system that can communicate with peripheral devices, such as personal computers, lin/j2602, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins, and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8 or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with the uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 15 bps to 1 mbps at 16 mips ? 4-deep, first-in-first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9 th bit = 1 ) ? transmit and receive interrupts ? loopback mode for diagnostic support ? support for sync and break characters ? supports automatic baud rate detection ?irda ? encoder and decoder logic ? 16x baud clock output for irda support a simplified block diagram of the uart is shown in figure 17-1. the uart module consists of these key important hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 17-1: uart simplified block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 21. ?uart? (ds39708). the information in this data sheet supersedes the information in the frm. uxrx irda ? hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts/ bclkx baud rate generator note: the uart inputs and outputs must all be assigned to available rpn/rpin pins before use. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 226 ? 2010 microchip technology inc. 17.1 uart baud rate generator (brg) the uart module includes a dedicated, 16-bit baud rate generator. the uxbrg register controls the period of a free-running, 16-bit timer. equation 17-1 shows the formula for computation of the baud rate with brgh = 0 . equation 17-1: uart baud rate with brgh = 0 (1,2) example 17-1 shows the calculation of the baud rate error for the following conditions: ?f cy = 4 mhz ? desired baud rate = 9600 the maximum baud rate (brgh = 0 ) possible is f cy /16 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(16 * 65536). equation 17-2 shows the formula for computation of the baud rate with brgh = 1 . equation 17-2: uart baud rate with brgh = 1 (1,2) the maximum baud rate (brgh = 1 ) possible is f cy /4 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(4 * 65536). writing a new value to the uxbrg register causes the brg timer to be reset (cleared). this ensures the brg does not wait for a timer overflow before generating the new baud rate. example 17-1: baud rate erro r calculation (brgh = 0 ) (1) note 1: f cy denotes the instruction cycle clock frequency (f osc /2 ). 2: based on f cy = f osc /2; doze mode and pll are disabled. baud rate = f cy 16 ? (uxbrg + 1) uxbrg = f cy 16 ? baud rate ? 1 note 1: f cy denotes the instruction cycle clock frequency . 2: based on f cy = f osc /2; doze mode and pll are disabled. baud rate = f cy 4 ? (uxbrg + 1) uxbrg = f cy 4 ? baud rate ? 1 note: based on f cy = f osc /2; doze mode and pll are disabled. desired baud rate = f cy /(16 (brgx + 1)) solving for brgx value: brgx = ((f cy /desired baud rate)/16) ? 1 brgx = ((4000000/9600)/16) ? 1 brgx = 25 calculated baud rate = 4000000/(16 (25 + 1)) = 9615 error = (calculated baud rate ? desired baud rate) desired baud rate = (9615 ? 9600)/9600
? 2010 microchip technology inc. ds39975a-page 227 pic24fj256gb210 family 17.2 transmitting in 8-bit data mode 1. set up the uart: a) write appropriate values for data, parity and stop bits. b) write appropriate baud rate value to the uxbrg register. c) set up transmit and receive interrupt enable and priority bits. 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt two cycles after being set). 4. write a data byte to the lower byte of uxtxreg word. the value will be immediately transferred to the transmit shift register (tsr) and the serial bit stream will start shifting out with the next rising edge of the baud clock. 5. alternately, the data byte may be transferred while utxen = 0 and then the user may set utxen. this will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 6. a transmit interrupt will be generated as per interrupt control bit, utxiselx. 17.3 transmitting in 9-bit data mode 1. set up the uart (as described in section 17.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write uxtxreg as a 16-bit value only. 5. a word write to uxtxreg triggers the transfer of the 9-bit data to the tsr. the serial bit stream will start shifting out with the first rising edge of the baud clock. 6. a transmit interrupt will be generated as per the setting of control bit, utxiselx. 17.4 break and sync transmit sequence the following sequence will send a message frame header, made up of a break, followed by an auto-baud sync byte. 1. configure the uart for the desired mode. 2. set utxen and utxbrk to set up the break character. 3. load the uxtxreg with a dummy character to initiate transmission (value is ignored). 4. write ?55h? to uxtxreg; this loads the sync character into the transmit fifo. 5. after the break has been sent, the utxbrk bit is reset by hardware. the sync character now transmits. 17.5 receiving in 8-bit or 9-bit data mode 1. set up the uart (as described in section 17.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. a receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, urxiselx. 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read uxrxreg. the act of reading the uxrxreg character will move the next character to the top of the receive fifo, including a new set of perr and ferr values. 17.6 operation of uxcts and uxrts control pins uartx clear to send (uxcts ) and request to send (uxrts ) are the two hardware controlled pins that are associated with the uart module. these two pins allow the uart to operate in simplex and flow control mode. they are implemented to control the transmis- sion and reception between the data terminal equipment (dte). the uen<1:0> bits in the uxmode register configure these pins. 17.7 infrared support the uart module provides two types of infrared uart support: one is the irda clock output to support an external irda encoder and decoder device (legacy module support), and the other is the full implementa- tion of the irda encoder and decoder. note that because the irda modes require a 16x baud clock, they will only work when the brgh bit (uxmode<3>) is ? 0 ?. 17.7.1 irda clock output for external irda support to support external irda encoder and decoder devices, the bclkx pin (same as the uxrts pin) can be configured to generate the 16x baud clock. with uen<1:0> = 11 , the bclkx pin will output the 16x baud clock if the uart module is enabled. it can be used to support the irda codec chip. 17.7.2 built-in irda encoder and decoder the uart has full implementation of the irda encoder and decoder as part of the uart module. the built-in irda encoder and decoder functionality is enabled using the iren bit (uxmode<12>). when enabled (iren = 1 ), the receive pin (uxrx) acts as the input from the infrared receiver. the transmit pin (uxtx) acts as the output to the infrared transmitter.
pic24fj256gb210 family ds39975a-page 228 ? 2010 microchip technology inc. register 17-1: uxmode: uartx mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten (1) ? usidl iren (2) rtsmd ? uen1 uen0 bit 15 bit 8 r/w-0, hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit (1) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption is minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (2) 1 = irda encoder and decoder are enabled 0 = irda encoder and decoder are disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and bclkx pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclkx pins are controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = no wake-up is enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h); cleared in hardware upon completion 0 = baud rate measurement is disabled or completed note 1: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information. 2: this feature is only available for the 16x brg mode (brgh = 0 ).
? 2010 microchip technology inc. ds39975a-page 229 pic24fj256gb210 family bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = high-speed mode (4 brg clock cycles per bit) 0 = standard-speed mode (16 brg clock cycles per bit) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 17-1: uxmode: uartx mode register (continued) note 1: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information. 2: this feature is only available for the 16x brg mode (brgh = 0 ).
pic24fj256gb210 family ds39975a-page 230 ? 2010 microchip technology inc. register 17-2: uxsta: uartx status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 hc r/w-0 r-0, hsc r-1, hsc utxisel1 utxinv (1) utxisel0 ? utxbrk utxen (2) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1, hsc r-0, hsc r-0, hsc r/c-0, hs r-0, hsc urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown hs = hardware settable bit hc = hardware clearable bit bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr), and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: irda ? encoder transmit polarity inversion bit (1) iren = 0 : 1 = uxtx is idle ? 0 ? 0 = uxtx is idle ? 1 ? iren = 1 : 1 = uxtx is idle ? 1 ? 0 = uxtx is idle ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission is disabled or completed bit 10 utxen: transmit enable bit (2) 1 = transmit is enabled, uxtx pin controlled by uartx 0 = transmit is disabled, any pending transmission is aborted and the buffer is reset; uxtx pin is controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and the transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued note 1: value of bit only affects the transmit properties of the module when the irda ? encoder is enabled (iren = 1 ). 2: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information.
? 2010 microchip technology inc. ds39975a-page 231 pic24fj256gb210 family bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on an rsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on an rsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the rsr to the receive buffer; receive buffer has one or more characters bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled if 9-bit mode is not selected, this does not take effect. 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (clear/read-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed (clearing a previously set oerr bit ( 1 ? 0 transition); will reset the receiver buffer and the rsr to the empty state bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 17-2: uxsta: uartx status and control register (continued) note 1: value of bit only affects the transmit properties of the module when the irda ? encoder is enabled (iren = 1 ). 2: if uarten = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 232 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 233 pic24fj256gb210 family 18.0 universal serial bus with on-the-go support (usb otg) pic24fj256gb210 family devices contain a full-speed and low-speed compatible, on-the-go (otg) usb serial interface engine (sie). the otg capability allows the device to act either as a usb peripheral device or as a usb embedded host with limited host capabilities. the otg capability allows the device to dynamically switch from device to host operation using otg?s host negotiation protocol (hnp). for more details on otg operation, refer to the ? on-the-go supplement? to the ? usb 2.0 specifica- tion ?, published by the usb-if. for more details on usb operation, refer to the ? universal serial bus specification ?, v2.0. the usb otg module offers these features: ? usb functionality in device and host modes, and otg capabilities for application-controlled mode switching ? software-selectable module speeds of full speed (12 mbps) or low speed (1.5 mbps, available in host mode only) ? support for all four usb transfer types: control, interrupt, bulk and isochronous ? 16 bidirectional endpoints for a total of 32 unique endpoints ? dma interface for data ram access ? queues up to sixteen unique endpoint transfers without servicing ? integrated, on-chip usb transceiver with support for off-chip transceivers via a digital interface ? integrated v bus generation with on-chip comparators and boost generation, and support of external v bus comparators and regulators through a digital interface ? configurations for on-chip bus pull-up and pull-down resistors a simplified block diagram of the usb otg module is shown in figure 18-1. the usb otg module can function as a usb peripheral device or as a usb host, and may dynamically switch between device and host modes under software control. in either mode, the same data paths and buffer descriptors (bds) are used for the transmission and reception of data. in discussing usb operation, this section will use a controller-centric nomenclature for describing the direc- tion of the data transfer between the microcontroller and the usb. rx (receive) will be used to describe transfers that move data from the usb to the microcontroller and tx (transmit) will be used to describe transfers that move data from the microcontroller to the usb. table 18-1 shows the relationship between data direction in this nomenclature and the usb tokens exchanged. table 18-1: controller-centric data direction for usb host or target this chapter presents the most basic operations needed to implement usb otg functionality in an application. a complete and detailed discussion of the usb protocol and its otg supplement are beyond the scope of this data sheet. it is assumed that the user already has a basic understanding of usb architecture and the latest version of the protocol. not all steps for proper usb operation (such as device enumeration) are presented here. it is recommended that application developers use an appropriate device driver to implement all of the necessary features. microchip provides a number of application-specific resources, such as usb firmware and driver support. refer to www.microchip.com/usb for the latest firmware and driver support. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 27. ?usb on-the-go (otg)? (ds39721). the information in this data sheet supersedes the information in the frm. usb mode direction rx tx device out or setup in host in out or setup
pic24fj256gb210 family ds39975a-page 234 ? 2010 microchip technology inc. figure 18-1: usb otg module block diagram 48 mhz usb clock d+ (1) d- (1) usbid (1) v bus (1) transceiver v buson (1) comparators usb srp charge srp discharge registers and control interface voltage system ram full-speed pull-up host pull-down host pull-down note 1: pins are multiplexed with digital i/o and other device features. vmio (1) vpio (1) dmh (1) dph (1) dmln (1) dpln (1) rcv (1) v bus boost assist external transceiver interface usboen (1) v cmpst 1/v busvld (1) v cmpst 2/sessvld (1) v busst (1) v cpcon (1) sie usb sessend (1) transceiver power 3.3v v usb
? 2010 microchip technology inc. ds39975a-page 235 pic24fj256gb210 family 18.1 hardware configuration 18.1.1 device mode 18.1.1.1 d+ pull-up resistor pic24fj256gb210 family devices have a built-in 1.5 k ? resistor on the d+ line that is available when the microcontroller is operating in device mode. this is used to signal an external host that the device is operating in full-speed device mode. it is engaged by setting the usben bit (u1con<0>). if the otgen bit (u1otgcon<2>) is set, then the d+ pull-up is enabled through the dppulup bit (u1otgcon<7>). alternatively, an external resistor may be used on d+, as shown in figure 18-2. figure 18-2: external pull-up for full-speed device mode 18.1.1.2 power modes many usb applications will likely have several different sets of power requirements and configuration. the most common power modes encountered are: ?bus power only mode ? self-power only mode ? dual power with self-power dominance bus power only mode (figure 18-3) is effectively the simplest method. all power for the application is drawn from the usb. to meet the inrush current requirements of the ?usb 2.0 otg specification? , the total effective capac- itance appearing across v bus and ground must be no more than 10 ? f. in the usb suspend mode, devices must consume no more than 2.5 ma from the 5v v bus line of the usb cable. during the usb suspend mode, the d+ or d- pull-up resistor must remain active, which will consume some of the allowed suspend current. in self-power only mode (figure 18-4), the usb application provides its own power, with very little power being pulled from the usb. note that an attach indication is added to indicate when the usb has been connected and the host is actively powering v bus . to meet compliance specifications, the usb module (and the d+ or d- pull-up resistor) should not be enabled until the host actively drives v bus high. one of the 5.5v tolerant i/o pins may be used for this purpose. the application should never source any current onto the 5v v bus pin of the usb cable. the dual power mode with self-power dominance (figure 18-5) allows the application to use internal power primarily, but switch to power from the usb when no internal power is available. dual power devices must also meet all of the special requirements for inrush current and suspend mode current previ- ously described, and must not enable the usb module until v bus is driven high. figure 18-3: bus power only figure 18-4: self-power only pic ? mcu host controller/hub v usb d+ d- 1.5 k ? v dd v usb v ss v bus ~5v 3.3v low i q regulator attach sense v bus 100 ? v dd v usb v ss v self ~3.3v attach sense 100 k ? 100 ? v bus ~5v v bus
pic24fj256gb210 family ds39975a-page 236 ? 2010 microchip technology inc. figure 18-5: dual power example 18.1.2 host and otg modes 18.1.2.1 d+ and d- pull-down resistors pic24fj256gb210 family devices have a built-in 15 k ? pull-down resistor on the d+ and d- lines. these are used in tandem to signal to the bus that the micro- controller is operating in host mode. they are engaged by setting the hosten bit (u1con<3>). if the otgen bit (u1otgcon<2>) is set, then these pull-downs are enabled by setting the dppuldwn and dmpuldwn bits (u1otgcon<5:4>). 18.1.2.2 power configurations in host mode, as well as host mode in on-the-go operation, the ?usb 2.0 otg specification? requires that the host application should supply power on v bus . since the microcontroller is running below v bus , and is not able to source sufficient current, a separate power supply must be provided. when the application is always operating in host mode, a simple circuit can be used to supply v bus and regulate current on the bus (figure 18-6). for otg operation, it is necessary to be able to turn v bus on or off as needed, as the microcontroller switches between device and host modes. a typical example using an external charge pump is shown in figure 18-7. figure 18-6: host interface example v dd v usb v bus v ss attach sense v bus v self 100 ? ~3.3v ~5v 100 k ? 3.3v low i q regulator a/d pin v usb v dd v ss d+ d- v bus id d+ d- v bus id gnd +3.3v +3.3v polymer ptc thermal fuse micro a/b connector 150 f 2 k ? 2 k ? 0.1 f, 3.3v +5v pic ? mcu
? 2010 microchip technology inc. ds39975a-page 237 pic24fj256gb210 family figure 18-7: otg interface example 18.1.2.3 v bus voltage generation with external devices when operating as a usb host, either as an a-device in an otg configuration or as an embedded host, v bus must be supplied to the attached device. pic24fj256gb210 family devices have an internal v bus boost assist to help generate the required 5v v bus from the available voltages on the board. this is comprised of a simple pwm output to control a switch mode power supply, and built-in comparators to monitor output voltage and limit current. to enable voltage generation: 1. verify that the usb module is powered (u1pwrc<0> = 1 ) and that the v bus discharge is disabled (u1otgcon<0> = 0 ). 2. set the pwm period (u1pwmrrs<7:0>) and duty cycle (u1pwmrrs<15:8>) as required. 3. select the required polarity of the output signal based on the configuration of the external circuit with the pwmpol bit (u1pwmcon<9>). 4. select the desired target voltage using the vbuschg bit (u1otgcon<1>). 5. enable the pwm counter by setting the cnten bit to ? 1 ? (u1pwmcon<8>). 6. enable the pwm module by setting the pwmen bit (u1pwmcon<15>) to ? 1 ?. 7. enable the v bus generation circuit (u1otgcon<3> = 1 ). 18.1.3 using an external interface some applications may require the usb interface to be isolated from the rest of the system. pic24fj256gb210 family devices include a complete interface to communicate with and control an external usb transceiver, including the control of data line pull-ups and pull-downs. the v bus voltage generation control circuit can also be configured for different v bus generation topologies. refer to the ? pic24f family reference manual ?, section 27. ?usb on-the-go (otg)? for information on using the external interface. 18.1.4 calculating transceiver power requirements the usb transceiver consumes a variable amount of current depending on the characteristic impedance of the usb cable, the length of the cable, the v usb supply voltage and the actual data patterns moving across the usb cable. longer cables have larger capacitances and consume more total energy when switching output states. the total transceiver current consumption will be application-specific. equation 18-1 can help estimate how much current actually may be required in full-speed applications. refer to the ? pic24f family reference manual ?, section 27. ?usb on-the-go (otg)? for a complete discussion on transceiver power consumption. i/o i/o v ss d+ d- v bus id d+ d- v bus id gnd micro a/b connector 40 k ? 4.7 f v dd pic ? mcu 10 f v in select shnd pgood mcp1253 v out c+ c- gnd 1 f note: this section describes the general process for v bus voltage generation and control. please refer to the ? pic24f family reference manual? for additional examples.
pic24fj256gb210 family ds39975a-page 238 ? 2010 microchip technology inc. equation 18-1: estimating usb t ransceiver current consumption legend: v usb ? voltage applied to the v usb pin in volts (3.0v to 3.6v). p zero ? percentage (in decimal) of the in traffic bits sent by the pic ? microcontroller that are a value of ? 0 ?. p in ? percentage (in decimal) of total bus bandwidth that is used for in traffic. l cable ? length (in meters) of the usb cable. the ?usb 2.0 otg specification? requires that full-speed applications use cables no longer than 5m. i pullup ? current which the nominal, 1.5 k ? pull-up resistor (when enabled) must supply to the usb cable. 40 ma ? v usb ? p zero ? p in ? l cable ixcvr = 3.3v ? 5m + i pullup
? 2010 microchip technology inc. ds39975a-page 239 pic24fj256gb210 family 18.2 usb buffer descriptors and the bdt endpoint buffer control is handled through a structure called the buffer descriptor table (bdt). this provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. the bdt can be located in any available, 512-byte aligned block of data ram. the bdt pointer (u1bdtp1) contains the upper address byte of the bdt and sets the location of the bdt in ram. the user must set this pointer to indicate the table?s location. the bdt is composed of buffer descriptors (bds) which are used to define and control the actual buffers in the usb ram space. each bd consists of two, 16-bit ?soft? (non-fixed-address) registers, bdnstat and bdnadr, where n represents one of the 64 possible bds (range of 0 to 63). bdnstat is the status register for bdn, while bdnadr specifies the starting address for the buffer associated with bdn. depending on the endpoint buffering configuration used, there are up to 64 sets of buffer descriptors, for a total of 256 bytes. at a minimum, the bdt must be at least 8 bytes long. this is because the ?usb 2.0 otg specification? mandates that every device must have endpoint 0 with both input and output for initial setup. endpoint mapping in the bdt is dependent on three variables: ? endpoint number (0 to 15) ? endpoint direction (rx or tx) ? ping-pong settings (u1cnfg1<1:0>) figure 18-8 illustrates how these variables are used to map endpoints in the bdt. in host mode, only endpoint 0 buffer descriptors are used. all transfers utilize the endpoint 0 buffer descrip- tor and endpoint control register (u1ep0). for received packets, the attached device?s source endpoint is indicated by the value of endpt<3:0> in the usb status register (u1stat<7:4>). for transmitted packets, the attached device?s destination endpoint is indicated by the value written to the token register (u1tok). figure 18-8: bdt mapping for endpoint buffering modes note: since bdnadr is a 16-bit register, only the first 64 kbytes of ram can be accessed by the usb module. ep1 tx even ep1 rx even ep1 rx odd ep1 tx odd descriptor descriptor descriptor descriptor ep1 tx ep15 tx ep1 rx ep0 rx ppb<1:0> = 00 ep0 tx ep1 tx no ping-pong ep15 tx ep0 tx ep0 rx even ppb<1:0> = 01 ep0 rx odd ep1 rx ping-pong buffer ep15 tx odd ep0 tx even ep0 rx even ppb<1:0> = 10 ep0 rx odd ep0 tx odd ping-pong buffers descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor descriptor note: memory area is not shown to scale. descriptor descriptor descriptor descriptor buffers on ep0 out on all eps ep1 tx even ep1 rx even ep1 rx odd ep1 tx odd descriptor descriptor descriptor descriptor ep15 tx odd ep0 rx ppb<1:0> = 11 ep0 tx ping-pong buffers descriptor descriptor descriptor on all other eps except ep0 total bdt space: total bdt space: total bdt space: total bdt space: 128 bytes 132 bytes 256 bytes 248 bytes
pic24fj256gb210 family ds39975a-page 240 ? 2010 microchip technology inc. bds have a fixed relationship to a particular endpoint, depending on the buffering configuration. table 18-2 provides the mapping of bds to endpoints. this rela- tionship also means that gaps may occur in the bdt if endpoints are not enabled contiguously. this, theoreti- cally, means that the bds for disabled endpoints could be used as buffer space. in practice, users should avoid using such spaces in the bdt unless a method of validating bd addresses is implemented. 18.2.1 buffer ownership because the buffers and their bds are shared between the cpu and the usb module, a simple semaphore mechanism is used to distinguish which is allowed to update the bd and associated buffers in memory. this is done by using the uown bit as a semaphore to distinguish which is allowed to update the bd and associated buffers in memory. uown is the only bit that is shared between the two configurations of bdnstat. when uown is clear, the bd entry is ?owned? by the microcontroller core. when the uown bit is set, the bd entry and the buffer memory are ?owned? by the usb peripheral. the core should not modify the bd or its corresponding data buffer during this time. note that the microcontroller core can still read bdnstat while the sie owns the buffer and vice versa. the buffer descriptors have a different meaning based on the source of the register update. register 18-1 and register 18-2 show the differences in bdnstat depending on its current ?ownership?. when uown is set, the user can no longer depend on the values that were written to the bds. from this point, the usb module updates the bds as necessary, over- writing the original bd values. the bdnstat register is updated by the sie with the token pid and the transfer count is updated. 18.2.2 dma interface the usb otg module uses a dedicated dma to access both the bdt and the endpoint data buffers. since part of the address space of the dma is dedi- cated to the buffer descriptors, a portion of the memory connected to the dma must comprise a contiguous address space properly mapped for the access by the module. table 18-2: assignment of buffer descriptors for the different buffering modes endpoint bds assigned to endpoint mode 0 (no ping-pong) mode 1 (ping-pong on ep0 out) mode 2 (ping-pong on all eps) mode 3 (ping-pong on all other eps, except ep0) out in out in out in out in 0 0 1 0 (e), 1 (o) 2 0 (e), 1 (o) 2 (e), 3 (o) 0 1 1 2 3 3 4 4 (e), 5 (o) 6 (e), 7 (o) 2 (e), 3 (o) 4 (e), 5 (o) 2 4 5 5 6 8 (e), 9 (o) 10 (e), 11 (o) 6 (e), 7 (o) 8 (e), 9 (o) 3 6 7 7 8 12 (e), 13 (o) 14 (e), 15 (o) 10 (e), 11 (o) 12 (e), 13 (o) 4 8 9 9 10 16 (e), 17 (o) 18 (e), 19 (o) 14 (e), 15 (o) 16 (e), 17 (o) 5 10 11 11 12 20 (e), 21 (o) 22 (e), 23 (o) 18 (e), 19 (o) 20 (e), 21 (o) 6 12 13 13 14 24 (e), 25 (o) 26 (e), 27 (o) 22 (e), 23 (o) 24 (e), 25 (o) 7 14 15 15 16 28 (e), 29 (o) 30 (e), 31 (o) 26 (e), 27 (o) 28 (e), 29 (o) 8 16 17 17 18 32 (e), 33 (o) 34 (e), 35 (o) 30 (e), 31 (o) 32 (e), 33 (o) 9 18 19 19 20 36 (e), 37 (o) 38 (e), 39 (o) 34 (e), 35 (o) 36 (e), 37 (o) 10 20 21 21 22 40 (e), 41 (o) 42 (e), 43 (o) 38 (e), 39 (o) 40 (e), 41 (o) 11 22 23 23 24 44 (e), 45 (o) 46 (e), 47 (o) 42 (e), 43 (o) 44 (e), 45 (o) 12 24 25 25 26 48 (e), 49 (o) 50 (e), 51 (o) 46 (e), 47 (o) 48 (e), 49 (o) 13 26 27 27 28 52 (e), 53 (o) 54 (e), 55 (o) 50 (e), 51 (o) 52 (e), 53 (o) 14 28 29 29 30 56 (e), 57 (o) 58 (e), 59 (o) 54 (e), 55 (o) 56 (e), 57 (o) 15 30 31 31 32 60 (e), 61 (o) 62 (e), 63 (o) 58 (e), 59 (o) 60 (e), 61 (o) legend: (e) = even transaction buffer, (o) = odd transaction buffer
? 2010 microchip technology inc. ds39975a-page 241 pic24fj256gb210 family register 18-1: bdnstat: buffer descriptor n status register prototype, usb mode (bd0stat through bd63stat) r/w-x r/w-x r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc uown dts pid3 pid2 pid1 pid0 bc9 bc8 bit 15 bit 8 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r /w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uown: usb own bit 1 = the usb module owns the bd and its corresponding buffer; the cpu must not modify the bd or the buffer bit 14 dts: data toggle packet bit 1 = data 1 packet 0 = data 0 packet bit 13-10 pid<3:0>: packet identifier bits (written by the usb module) in device mode: represents the pid of the received token during the last transfer. in host mode: represents the last returned pid or the transfer status indicator. bit 9-0 bc<9:0>: byte count bits this represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. upon completion, the byte count is updated by the usb module with the actual number of bytes transmitted or received.
pic24fj256gb210 family ds39975a-page 242 ? 2010 microchip technology inc. register 18-2: bdnstat: buffer descriptor n status register prototype, cpu mode (bd0stat through bd63stat) r/w-x r/w-x r-0 r-0 r/w-x r/w-x r/w-x, hsc r/w-x, hsc uown dts (1) reserved reserved dtsen bstall bc9 bc8 bit 15 bit 8 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r /w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?r? = reserved bit x = bit is unknown bit 15 uown: usb own bit 0 = the microcontroller core owns the bd and its corresponding buffer; the usb module ignores all other fields in the bd bit 14 dts: data toggle packet bit (1) 1 = data 1 packet 0 = data 0 packet bit 13-12 reserved: maintain as ? 0 ? bit 11 dtsen: data toggle synchronization enable bit 1 = data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = no data toggle synchronization is performed bit 10 bstall: buffer stall enable bit 1 = buffer stall enabled; stall handshake issued if a token is received that would use the bd in the given location (uown bit remains set, bd value is unchanged); corresponding epstall bit will get set on any stall handshake 0 = buffer stall disabled bit 9-0 bc<9:0>: byte count bits this represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. upon completion, the byte count is updated by the usb module with the actual number of bytes transmitted or received. note 1: this bit is ignored unless dtsen = 1 .
? 2010 microchip technology inc. ds39975a-page 243 pic24fj256gb210 family 18.3 usb interrupts the usb otg module has many conditions that can be configured to cause an interrupt. all interrupt sources use the same interrupt vector. figure 18-9 shows the interrupt logic for the usb module. there are two layers of interrupt registers in the usb module. the top level consists of overall usb status interrupts; these are enabled and flagged in the u1ie and u1ir registers, respectively. the second level consists of usb error conditions, which are enabled and flagged in the u1eir and u1eie registers. an interrupt condition in any of these triggers a usb error interrupt flag (uerrif) in the top level. interrupts may be used to trap routine events in a usb transaction. figure 18-10 provides some common events within a usb frame and their corresponding interrupts. figure 18-9: usb otg interrupt funnel dmaef dmaee btoef btoee dfn8ef dfn8ee crc16ef crc16ee crc5ef (eofef) crc5ee (eofee) pidef pidee attachif attachie resumeif resumeie idleif idleie trnif trnie sofif sofie urstif (detachif) urstie (detachie) (uerrif) uerrie set usb1if stallif stallie btsef btsee t1msecif timsecie lstateif lstateie actvif actvie sesvdif sesvdie sesendif sesendie vbusvdif vbusvdie idif idie second level (usb error) interrupts top level (usb status) interrupts top level (usb otg) interrupts
pic24fj256gb210 family ds39975a-page 244 ? 2010 microchip technology inc. 18.3.1 clearing usb otg interrupts unlike device level interrupts, the usb otg interrupt status flags are not freely writable in software. all usb otg flag bits are implemented as hardware set only bits. additionally, these bits can only be cleared in software by writing a ? 1 ? to their locations (i.e., perform- ing a mov type instruction). writing a ? 0 ? to a flag bit (i.e., a bclr instruction) has no effect. figure 18-10: example of a usb transaction and interrupt events 18.4 device mode operation the following section describes how to perform a com- mon device mode task. in device mode, usb transfers are performed at the transfer level. the usb module automatically performs the status phase of the transfer. 18.4.1 enabling device mode 1. reset the ping-pong buffer pointers by setting, then clearing, the ping-pong buffer reset bit, ppbrst (u1con<1>). 2. disable all interrupts (u1ie and u1eie = 00h). 3. clear any existing interrupt flags by writing ffh to u1ir and u1eir. 4. verify that v bus is present (non otg devices only). 5. enable the usb module by setting the usben bit (u1con<0>). 6. set the otgen bit (u1otgcon<2>) to enable otg operation. 7. enable the endpoint zero buffer to receive the first setup packet by setting the eprxen and ephshk bits for endpoint 0 (u1ep0<3,0> = 1 ). 8. power up the usb module by setting the usbpwr bit (u1pwrc<0>). 9. enable the d+ pull-up resistor to signal an attach by setting dppulup bit (u1otgcon<7>). note: throughout this data sheet, a bit that can only be cleared by writing a ? 1 ? to its loca- tion is referred to as ?write 1 to clear?. in register descriptions, this function is indicated by the descriptor, ?k?. usb reset sof reset setup data status sof setup token data ack out token empty data ack start-of-frame (sof) in token data ack sofif urstif 1ms frame differential data from host from host to h o s t from host to host from host from host from host to h o s t transaction control transfer (1) transaction complete note 1: the control transfer shown here is only an example showin g events that can occur for every transaction. typical control transfers will spread across multiple frames. set trnif set trnif set trnif
? 2010 microchip technology inc. ds39975a-page 245 pic24fj256gb210 family 18.4.2 receiving an in token in device mode 1. attach to a usb host and enumerate as described in chapter 9 of the ?usb 2.0 specification? . 2. create a data buffer and populate it with the data to send to the host. 3. in the appropriate (even or odd) tx bd for the desired endpoint: a) set up the status register (bdnstat) with the correct data toggle (data0/1) value and the byte count of the data buffer. b) set up the address register (bdnadr) with the starting address of the data buffer. c) set the uown bit of the status register to ? 1 ?. 4. when the usb module receives an in token, it automatically transmits the data in the buffer. upon completion, the module updates the status register (bdnstat) and sets the transfer complete interrupt flag, trnif (u1ir<3>). 18.4.3 receiving an out token in device mode 1. attach to a usb host and enumerate as described in chapter 9 of the ?usb 2.0 specification? . 2. create a data buffer with the amount of data you are expecting from the host. 3. in the appropriate (even or odd) tx bd for the desired endpoint: a) set up the status register (bdnstat) with the correct data toggle (data0/1) value and the byte count of the data buffer. b) set up the address register (bdnadr) with the starting address of the data buffer. c) set the uown bit of the status register to ? 1 ?. 4. when the usb module receives an out token, it automatically receives the data sent by the host to the buffer. upon completion, the module updates the status register (bdnstat) and sets the transfer complete interrupt flag, trnif (u1ir<3>). 18.5 host mode operation the following sections describe how to perform common host mode tasks. in host mode, usb transfers are invoked explicitly by the host software. the host software is responsible for the acknowledge portion of the transfer. also, all transfers are performed using the endpoint 0 control register (u1ep0) and buffer descriptors. 18.5.1 enable host mode and discover a connected device 1. enable host mode by setting the hosten bit (u1con<3>). this causes the host mode con- trol bits in other usb otg registers to become available. 2. enable the d+ and d- pull-down resistors by setting the dppuldwn and dmpuldwn bits (u1otgcon<5:4>). disable the d+ and d- pull-up resistors by clearing the dppulup and dmpulup bits (u1otgcon<7:6>). 3. at this point, sof generation begins with the sof counter loaded with 12,000. eliminate noise on the usb by clearing the sofen bit (u1con<0>) to disable start-of-frame packet generation. 4. enable the device attached interrupt by setting the attachie bit (u1ie<6>). 5. wait for the device attached interrupt (u1ir<6> = 1 ). this is signaled by the usb device changing the state of d+ or d- from ? 0 ? to ? 1 ? (se0 to j-state). after it occurs, wait 100 ms for the device power to stabilize. 6. check the state of the jstate and se0 bits in u1con. if the jstate bit (u1con<7>) is ? 0 ?, the connecting device is low speed. if the con- necting device is low speed, set the low lspden and lspd bits (u1addr<7>, and u1ep0<7>) to enable low-speed operation. 7. reset the usb device by setting the usbrst bit (u1con<4>) for at least 50 ms, sending reset signaling on the bus. after 50 ms, terminate the reset by clearing usbrst. 8. in order to keep the connected device from going into suspend, enable the sof packet generation by setting the sofen bit. 9. wait 10 ms for the device to recover from reset. 10. perform enumeration as described by chapter 9 of the ?usb 2.0 specification? .
pic24fj256gb210 family ds39975a-page 246 ? 2010 microchip technology inc. 18.5.2 complete a control transaction to a connected device 1. follow the procedure described in section 18.5.1 ?enable host mode and discover a connected device? to discover a device. 2. set up the endpoint control register for bidirectional control transfers by writing 0dh to u1ep0 (this sets the epcondis, eptxen and ephshk bits). 3. place a copy of the device framework setup command in a memory buffer. see chapter 9 of the ?usb 2.0 specification? for information on the device framework command set. 4. initialize the buffer descriptor (bd) for the current (even or odd) tx ep0 to transfer the eight bytes of command data for a device framework command (i.e., get device descriptor ): a) set the bd data buffer address (bd0adr) to the starting address of the 8-byte memory buffer containing the command. b) write 8008h to bd0stat (this sets the uown bit and sets a byte count of 8). 5. set the usb device address of the target device in the address register (u1addr<6:0>). after a usb bus reset, the device usb address will be zero. after enumeration, it will be set to another value between 1 and 127. 6. write d0h to u1tok; this is a setup token to endpoint 0, the target device?s default control pipe. this initiates a setup token on the bus, followed by a data packet. the device hand- shake is returned in the pid field of bd0stat after the packets are complete. when the usb module updates bd0stat, a transfer done interrupt is asserted (the trnif flag is set). this completes the setup phase of the setup transac- tion as referenced in chapter 9 of the ?usb 2.0 specification? . 7. to initiate the data phase of the setup transac- tion (i.e., get the data for the get device descriptor command), set up a buffer in memory to store the received data. 8. initialize the current (even or odd) rx or tx (rx for in, tx for out) ep0 bd to transfer the data. a) write c040h to bd0stat. this sets the uown, configures data toggle (dts) to data1 and sets the byte count to the length of the data buffer (64 or 40h in this case). b) set bd0adr to the starting address of the data buffer. 9. write the token register with the appropriate in or out token to endpoint 0, the target device?s default control pipe (e.g., write 90h to u1tok for an in token for a get device descriptor command). this initiates an in token on the bus followed by a data packet from the device to the host. when the data packet completes, the bd0stat is written and a transfer done interrupt is asserted (the trnif flag is set). for control transfers with a single packet data phase, this completes the data phase of the setup transac- tion as referenced in chapter 9 of the ?usb 2.0 specification? . if more data needs to be transferred, return to step 8. 10. to initiate the status phase of the setup transac- tion, set up a buffer in memory to receive or send the zero length status phase data packet. 11. initialize the current (even or odd) tx ep0 bd to transfer the status data: a) set the bdt buffer address field to the start address of the data buffer. b) write 8000h to bd0stat (set uown bit, configure dts to data0 and set byte count to 0). 12. write the token register with the appropriate in or out token to endpoint 0, the target device?s default control pipe (e.g., write 01h to u1tok for an out token for a get device descriptor command). this initiates an out token on the bus followed by a zero length data packet from the host to the device. when the data packet completes, the bd is updated with the handshake from the device and a transfer done interrupt is asserted (the trnif flag is set). this completes the status phase of the setup transaction as described in chapter 9 of the ?usb 2.0 specification? . note: only one control transaction can be performed per frame.
? 2010 microchip technology inc. ds39975a-page 247 pic24fj256gb210 family 18.5.3 send a full-speed bulk data transfer to a target device 1. follow the procedure described in section 18.5.1 ?enable host mode and discover a connected device? and section 18.5.2 ?complete a con- trol transaction to a connected device? to discover and configure a device. 2. to enable transmit and receive transfers with handshaking enabled, write 1dh to u1ep0. if the target device is a low-speed device, also set the lspd (u1ep0<7>) bit. if you want the hard- ware to automatically retry indefinitely if the target device asserts a nak on the transfer, clear the retry disable bit, retrydis (u1ep0<6>). 3. set up the bd for the current (even or odd) tx ep0 to transfer up to 64 bytes. 4. set the usb device address of the target device in the address register (u1addr<6:0>). 5. write an out token to the desired endpoint to u1tok. this triggers the module?s transmit state machines to begin transmitting the token and the data. 6. wait for the transfer done interrupt flag, trnif. this indicates that the bd has been released back to the microprocessor and the transfer has completed. if the retry disable bit is set, the handshake (ack, nak, stall or error (0fh)) is returned in the bd pid field. if a stall interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. if a detach interrupt occurs (se0 for more than 2.5 s), then the target has detached (u1ir<0> is set). 7. once the transfer done interrupt occurs (trnif is set), the bd can be examined and the next data packet queued by returning to step 2. 18.6 otg operation 18.6.1 session request protocol (srp) an otg a-device may decide to power down the v bus supply when it is not using the usb link through the session request protocol (srp). software may do this by clearing vbuson (u1otgcon<3>). when the v bus supply is powered down, the a-device is said to have ended a usb session. an otg a-device or embedded host may repower the v bus supply at any time (initiate a new session). an otg b-device may also request that the otg a-device repower the v bus supply (initiate a new session). this is accomplished via session request protocol (srp). prior to requesting a new session, the b-device must first check that the previous session has definitely ended. to do this, the b-device must check for two conditions: 1. v bus supply is below the session valid voltage, and 2. both d+ and d- have been low for at least 2 ms. the b-device will be notified of condition 1 by the sesendif (u1otgir<2>) interrupt. software will have to manually check for condition 2. the b-device may aid in achieving condition 1 by dis- charging the v bus supply through a resistor. software may do this by setting vbusdis (u1otgcon<0>). after these initial conditions are met, the b-device may begin requesting the new session. the b-device begins by pulsing the d+ data line. software should do this by setting dppulup (u1otgcon<7>). the data line should be held high for 5 to 10 ms. the b-device then proceeds by pulsing the v bus supply. software should do this by setting puvbus (u1cnfg2<4>). when an a-device detects srp sig- naling (either via the attachif (u1ir<6>) interrupt or via the sesvdif (u1otgir <3>) interrupt), the a-device must restore the v bus supply by either setting vbuson (u1otgcon<3>) or by setting the i/o port controlling the external power source. the b-device should not monitor the state of the v bus supply while performing v bus supply pulsing. when the b-device does detect that the v bus supply has been restored (via the sesvdif (u1otgir<3>) interrupt), the b-device must reconnect to the usb link by pulling up d+ or d- (via the dppulup or dmpulup). the a-device must complete the srp by driving usb reset signaling. note: usb speed, transceiver and pull-ups should only be configured during the mod- ule setup phase. it is not recommended to change these settings while the module is enabled. note: when the a-device powers down the v bus supply, the b-device must disconnect its pull-up resistor from power. if the device is self-powered, it can do this by clearing dppulup (u1otgcon<7>) and dmpulup (u1otgcon<6>).
pic24fj256gb210 family ds39975a-page 248 ? 2010 microchip technology inc. 18.6.2 host negotiation protocol (hnp) in usb otg applications, a dual role device (drd) is a device that is capable of being either a host or a peripheral. any otg drd must support host negotiation protocol (hnp). hnp allows an otg b-device to temporarily become the usb host. the a-device must first enable the b-device to follow hnp. refer to the ?on-the-go supplement? to the ?usb 2.0 specification? for more information regarding hnp. hnp may only be initiated at full speed. after being enabled for hnp by the a-device, the b-device requests being the host any time that the usb link is in suspend state, by simply indicating a discon- nect. this can be done in software by clearing dppulup and dmpulup. when the a-device detects the disconnect condition (via the urstif (u1ir<0>) interrupt), the a-device may allow the b-device to take over as host. the a-device does this by signaling con- nect as a full-speed function. software may accomplish this by setting dppulup. if the a-device responds instead with resume signaling, the a-device remains as host. when the b-device detects the connect condition (via attachif (u1ir<6>), the b-device becomes host. the b-device drives reset signaling prior to using the bus. when the b-device has finished in its role as host, it stops all bus activity and turns on its d+ pull-up resistor by setting dppulup. when the a-device detects a suspend condition (idle for 3 ms), the a-device turns off its d+ pull-up. the a-device may also power-down the v bus supply to end the session. when the a-device detects the connect condition (via attachif), the a-device resumes host operation and drives reset signaling. 18.6.3 external v bus comparators the external v bus comparator option is enabled by set- ting the uvcmpdis bit (u1cnfg2<1>). this disables the internal v bus comparators, removing the need to attach v bus to the microcontroller?s v bus pin. the external comparator interface uses either the v cmpst 1 and v cmpst 2 pins, or the v busvld , sessvld and sessend pins, based upon the setting of the uvcmpsel bit (u1cnfg2<5>). these pins are digital inputs and should be set in the following patterns (see table 18-3), based on the current level of the v bus voltage. table 18-3: external v bus comparator states if uvcmpsel = 0 v cmpst 1v cmpst 2bus condition 00 v bus < vb_sess_end 10 vb_sess_end < v bus < va_sess_vld 01 va_sess_vld < v bus < va_vbus_vld 11 v bus > vbus_vld if uvcmpsel = 1 v busvld sessvld sessend bus condition 00 1 v bus < vb_sess_end 00 0 vb_sess_end < v bus < va_sess_vld 01 0 va_sess_vld < v bus < va_vbus_vld 11 0 v bus > vbus_vld
? 2010 microchip technology inc. ds39975a-page 249 pic24fj256gb210 family 18.7 usb otg module registers there are a total of 37 memory mapped registers asso- ciated with the usb otg module. they can be divided into four general categories: ? usb otg module control (12) ? usb interrupt (7) ? usb endpoint management (16) ? usb v bus power control (2) this total does not include the (up to) 128 bd registers in the bdt. their prototypes, described in register 18-1 and register 18-2, are shown separately in section 18.2 ?usb buffer descriptors and the bdt? . with the exception of u1pwmcon and u1pwmrrs, all usb otg registers are implemented in the least significant byte of the register. bits in the upper byte are unimplemented and have no function. note that some registers are instantiated only in host mode, while other registers have different bit instantiations and functions in device and host modes. the registers described in the following sections are those that have bits with specific control and configura- tion features. the following registers are used for data or address values only: ? u1bdtp1: specifies the 256-word page in data ram used for the bdt; 8-bit value with bit 0 fixed as ? 0 ? for boundary alignment. ? u1frml and u1frmh: contains the 11-bit byte counter for the current data frame. ? u1pwmrrs: contains the 8-bit value for pwm duty cycle bits<15:8> and pwm period bits<7:0> for the v bus boost assist pwm module.
pic24fj256gb210 family ds39975a-page 250 ? 2010 microchip technology inc. 18.7.1 usb otg module control registers register 18-3: u1otgstat: usb otg st atus register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-0, hsc u-0 r-0, hsc u-0 r-0, hsc r-0, hsc u-0 r-0, hsc id ?lstate ? sesvd sesend ? vbusvd bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 id: id pin state indicator bit 1 = no plug is attached or a type b cable has been plugged into the usb receptacle 0 = a type a plug has been plugged into the usb receptacle bit 6 unimplemented: read as ? 0 ? bit 5 lstate: line state stable indicator bit 1 = the usb line state (as defined by se0 and jstate) has been stable for the previous 1 ms 0 = the usb line state has not been stable for the previous 1 ms bit 4 unimplemented: read as ? 0 ? bit 3 sesvd: session valid indicator bit 1 =the v bus voltage is above va_sess_vld (as defined in the ?usb 2.0 otg specification? ) on the a or b-device 0 =the v bus voltage is below va_sess_vld on the a or b-device bit 2 sesend: b session end indicator bit 1 =the v bus voltage is below vb_sess_end (as defined in the ?usb 2.0 otg specification? ) on the b-device 0 =the v bus voltage is above vb_sess_end on the b-device bit 1 unimplemented: read as ? 0 ? bit 0 vbusvd: a v bus valid indicator bit 1 =the v bus voltage is above va_vbus_vld (as defined in the ?usb 2.0 otg specification? ) on the a-device 0 =the v bus voltage is below va_vbus_vld on the a-device
? 2010 microchip technology inc. ds39975a-page 251 pic24fj256gb210 family register 18-4: u1otgcon: usb on-the-go control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn (1) dmpuldwn (1) vbuson (1) otgen (1) vbuschg (1) vbusdis (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor is enabled 0 = d+ data line pull-up resistor is disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor is enabled 0 = d- data line pull-up resistor is disabled bit 5 dppuldwn: d+ pull-down enable bit (1) 1 = d+ data line pull-down resistor is enabled 0 = d+ data line pull-down resistor is disabled bit 4 dmpuldwn: d- pull-down enable bit (1) 1 = d- data line pull-down resistor is enabled 0 = d- data line pull-down resistor is disabled bit 3 vbuson: v bus power-on bit (1) 1 =v bus line is powered 0 =v bus line is not powered bit 2 otgen: otg features enable bit (1) 1 = usb otg is enabled; all d+/d- pull-up and pull-down bits are enabled 0 = usb otg is disabled; d+/d- pull-up and pull-down bits are controlled in hardware by the settings of the hosten and u sben (u1con<3,0>) bits bit 1 vbuschg: v bus charge select bit (1) 1 =v bus line is set to charge to 3.3v 0 =v bus line is set to charge to 5v bit 0 vbusdis: v bus discharge enable bit (1) 1 =v bus line is discharged through a resistor 0 =v bus line is not discharged note 1: these bits are only used in host mode; do not use in device mode.
pic24fj256gb210 family ds39975a-page 252 ? 2010 microchip technology inc. register 18-5: u1pwrc: usb power control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0, hs u-0 u-0 r/w-0 u-0 u-0 r/w-0, hc r/w-0 uactpnd ? ? uslpgrd ? ? ususpnd usbpwr bit 7 bit 0 legend: hs = hardware settable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 uactpnd: usb activity pending bit 1 = module should not be suspended at the moment (requires the uslpgrd bit to be set) 0 = module may be suspended or powered down bit 6-5 unimplemented: read as ? 0 ? bit 4 uslpgrd: sleep/suspend guard bit 1 = indicate to the usb module that it is about to be suspended or powered down 0 = no suspend bit 3-2 unimplemented: read as ? 0 ? bit 1 ususpnd: usb suspend mode enable bit 1 = usb otg module is in suspend mode; usb clock is gated and the transceiver is placed in a low-power state 0 = normal usb otg operation bit 0 usbpwr: usb operation enable bit 1 = usb otg module is enabled 0 = usb otg module is disabled (1) note 1: do not clear this bit unless the hosten, usben and otgen bits (u1con<3,0> and u1otgcon<2>) are all cleared.
? 2010 microchip technology inc. ds39975a-page 253 pic24fj256gb210 family register 18-6: u1stat: usb status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc u-0 u-0 endpt3 endpt2 endpt1 endpt0 dir ppbi (1) ? ? bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 endpt<3:0>: number of the last endpoint activity bits (represents the number of the bdt updated by the last usb transfer.) 1111 = endpoint 15 1110 = endpoint 14 . . . 0001 = endpoint 1 0000 = endpoint 0 bit 3 dir: last bd direction indicator bit 1 = the last transaction was a transmit transfer (tx) 0 = the last transaction was a receive transfer (rx) bit 2 ppbi: ping-pong bd pointer indicator bit (1) 1 = the last transaction was to the odd bd bank 0 = the last transaction was to the even bd bank bit 1-0 unimplemented: read as ? 0 ? note 1: this bit is only valid for endpoints with available even and odd bd registers.
pic24fj256gb210 family ds39975a-page 254 ? 2010 microchip technology inc. register 18-7: u1con: usb cont rol register (device mode) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r-x, hsc r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? se0 pktdis ? hosten resume ppbrst usben bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6 se0: live single-ended zero flag bit 1 = single-ended zero is active on the usb bus 0 = no single-ended zero is detected bit 5 pktdis: packet transfer disable bit 1 = sie token and packet processing are disabled; automatically set when a setup token is received 0 = sie token and packet processing are enabled bit 4 unimplemented: read as ? 0 ? bit 3 hosten: host mode enable bit 1 = usb host capability is enabled; pull-downs on d+ and d- are activated in hardware 0 = usb host capability is disabled bit 2 resume: resume signaling enable bit 1 = resume signaling is activated 0 = resume signaling is disabled bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all ping-pong buffer pointers to the even bd banks 0 = ping-pong buffer pointers are not reset bit 0 usben: usb module enable bit 1 = usb module and supporting circuitry are enabled (device attached); d+ pull-up is activated in hardware 0 = usb module and supporting circuitry are disabled (device detached)
? 2010 microchip technology inc. ds39975a-page 255 pic24fj256gb210 family register 18-8: u1con: usb control register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r-x, hsc r-x, hsc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 tokbusy usbrst hosten resume ppbrst sofen bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 jstate: live differential receiver j-state flag bit 1 = j-state (differential ? 0 ? in low speed, differential ? 1 ? in full speed) is detected on the usb 0 = no j-state is detected bit 6 se0: live single-ended zero flag bit 1 = single-ended zero is active on the usb bus 0 = no single-ended zero is detected bit 5 tokbusy: token busy status bit 1 = token is being executed by the usb module in on-the-go state 0 = no token is being executed bit 4 usbrst: module reset bit 1 = usb reset has been generated for software reset; application must set this bit for 50 ms, then clear it 0 = usb reset is terminated bit 3 hosten: host mode enable bit 1 = usb host capability is enabled; pull-downs on d+ and d- are activated in hardware 0 = usb host capability is disabled bit 2 resume: resume signaling enable bit 1 = resume signaling is activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = resume signaling is disabled bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all ping-pong buffer pointers to the even bd banks 0 = ping-pong buffer pointers are not reset bit 0 sofen: start-of-frame enable bit 1 = start-of-frame token is sent every one 1 ms 0 = start-of-frame token is disabled
pic24fj256gb210 family ds39975a-page 256 ? 2010 microchip technology inc. register 18-9: u1addr: usb address register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden (1) addr6 addr5 addr4 addr3 addr2 addr1 addr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 lspden: low-speed enable indicator bit (1) 1 = usb module operates at low speed 0 = usb module operates at full speed bit 6-0 addr<6:0>: usb device address bits note 1: host mode only. in device mode, this bit is unimplemented and read as ? 0 ?. register 18-10: u1tok: usb token register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid3 pid2 pid1 pid0 ep3 ep2 ep1 ep0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 pid<3:0>: token type identifier bits 1101 = setup (tx) token type transaction (1) 1001 = in (rx) token type transaction (1) 0001 = out (tx) token type transaction (1) bit 3-0 ep<3:0>: token command endpoint address bits this value must specify a valid endpoint on the attached device. note 1: all other combinations are reserved and are not to be used.
? 2010 microchip technology inc. ds39975a-page 257 pic24fj256gb210 family register 18-11: u1sof: usb otg start-of-token threshold register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 cnt<7:0>: start-of-frame size bits value represents 10 + (packet size of n bytes). for example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet register 18-12: u1cnfg1: usb configuration register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 uteye uoemon (1) ? usbsidl ? ? ppb1 ppb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 uteye: usb eye pattern test enable bit 1 = eye pattern test is enabled 0 = eye pattern test is disabled bit 6 uoemon: usb oe monitor enable bit (1) 1 =oe signal is active; it indicates intervals during which the d+/d- lines are driving 0 =oe signal is inactive bit 5 unimplemented: read as ? 0 ? bit 4 usbsidl: usb otg stop in idle mode bit 1 = discontinue module operation when the device enters idle mode 0 = continue module operation in idle mode bit 3-2 unimplemented: read as ? 0 ? bit 1-0 ppb<1:0>: ping-pong buffers configuration bits 11 = even/odd ping-pong buffers are enabled for endpoints 1 to 15 10 = even/odd ping-pong buffers are enabled for all endpoints 01 = even/odd ping-pong buffers are enabled for out endpoint 0 00 = even/odd ping-pong buffers are disabled note 1: this bit is only active when the utrdis bit (u1cnfg2<0>) is set.
pic24fj256gb210 family ds39975a-page 258 ? 2010 microchip technology inc. register 18-13: u1cnfg2: usb configuration register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? uvcmpsel puvbus exti2cen uvbusdis (1) uvcmpdis (1) utrdis (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 uvcmpsel: v bus comparator external interface selection bit 1 =use v busvld , sessvld and sessend as comparator interface pins 0 =use v cmpst 1 and v cmpst 2 as comparator interface pins bit 4 puvbus: v bus pull-up enable bit 1 = pull-up on v bus pin is enabled 0 = pull-up on v bus pin is disabled bit 3 exti2cen: i 2 c? interface for external module control enable bit 1 = external module(s) is controlled via the i 2 c? interface 0 = external module(s) controlled via the dedicated pins bit 2 uvbusdis: on-chip 5v boost regulator builder disable bit (1) 1 = on-chip boost regulator builder is disabled; digital output control interface is enabled 0 = on-chip boost regulator builder is active bit 1 uvcmpdis: on-chip v bus comparator disable bit (1) 1 = on-chip charge v bus comparator is disabled; digital input status interface is enabled 0 = on-chip charge v bus comparator is active bit 0 utrdis: on-chip transceiver disable bit (1) 1 = on-chip transceiver is disabled; digital transceiver interface is enabled 0 = on-chip transceiver is active note 1: never change these bits while the usbpwr bit is set (u1pwrc<0> = 1 ).
? 2010 microchip technology inc. ds39975a-page 259 pic24fj256gb210 family 18.7.2 usb interrupt registers register 18-14: u1otgir: usb otg interrup t status register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs u-0 r/k-0, hs idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 idif: id state change indicator bit 1 = change in id state is detected 0 = no id state change is detected bit 6 t1msecif: 1 millisecond timer bit 1 = the 1 millisecond timer has expired 0 = the 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit 1 = usb line state (as defined by the se0 and jstate bits) has been stable for 1 ms, but different from the last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit 1 = activity on the d+/d- lines or v bus is detected 0 = no activity on the d+/d- lines or v bus is detected bit 3 sesvdif: session valid change indicator bit 1 =v bus has crossed va_sess_end (as defined in the ?usb 2.0 otg specification? ) (1) 0 =v bus has not crossed va_sess_end bit 2 sesendif: b-device v bus change indicator bit 1 =v bus change on b-device detected; v bus has crossed vb_sess_end (as defined in the ?usb 2.0 otg specification? ) (1) 0 =v bus has not crossed va_sess_end bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdif: a-device v bus change indicator bit 1 =v bus change on a-device is detected; v bus has crossed va_vbus_vld (as defined in the ?usb 2.0 otg specification? ) (1) 0 =no v bus change on a-device is detected note 1: v bus threshold crossings may be either rising or falling. note: individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
pic24fj256gb210 family ds39975a-page 260 ? 2010 microchip technology inc. register 18-15: u1otgie: usb otg interrup t enable register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 idie: id interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 5 lstateie: line state stable interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 actvie: bus activity interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 sesvdie: session valid interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 sesendie: b-device session end interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdie: a-device v bus valid interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled
? 2010 microchip technology inc. ds39975a-page 261 pic24fj256gb210 family register 18-16: u1ir: usb interrupt status register (device mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs u-0 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r-0 r/k-0, hs stallif ? resumeif idleif trnif sofif uerrif urstif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = a stall handshake was sent by the peripheral during the handshake phase of the transaction in device mode 0 = a stall handshake has not been sent bit 6 unimplemented: read as ? 0 ? bit 5 resumeif: resume interrupt bit 1 = a k-state is observed on the d+ or d- pin for 2.5 ? s (differential ? 1 ? for low speed, differential ? 0 ? for full speed) 0 = no k-state is observed bit 4 idleif: idle detect interrupt bit 1 = idle condition is detected (constant idle state of 3 ms or more) 0 = no idle condition is detected bit 3 trnif: token processing complete interrupt bit 1 = processing of the current token is complete; read the u1stat register for endpoint information 0 = processing of the current token is not complete; clear the u1stat register or load the next token from stat (clearing this bit causes the stat fifo to advance) bit 2 sofif: start-of-frame token interrupt bit 1 = a start-of-frame token is received by the peripheral or the start-of-frame threshold is reached by the host 0 = no start-of-frame token is received or threshold reached bit 1 uerrif : usb error condition interrupt bit (read-only) 1 = an unmasked error condition has occurred; only error states enabled in the u1eie register can set this bit 0 = no unmasked error condition has occurred bit 0 urstif: usb reset interrupt bit 1 = valid usb reset has occurred for at least 2.5 ? s; reset state must be cleared before this bit can be reasserted 0 = no usb reset has occurred. individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bitwise oper- ations to write to a single bit position will cause all set bits at the moment of the write to become cleared. note: individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
pic24fj256gb210 family ds39975a-page 262 ? 2010 microchip technology inc. register 18-17: u1ir: usb interrupt status register (host mode only) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r-0 r/k-0, hs stallif attachif resumeif idleif trnif sofif uerrif detachif bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = a stall handshake was sent by the peripheral device during the handshake phase of the transaction in device mode 0 = a stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit 1 = a peripheral attachment has been detected by the module; it is set if the bus state is not se0 and there has been no bus activity for 2.5 ? s 0 = no peripheral attacement has been detected bit 5 resumeif: resume interrupt bit 1 = a k-state is observed on the d+ or d- pin for 2.5 ? s (differential ? 1 ? for low speed, differential ? 0 ? for full speed) 0 = no k-state is observed bit 4 idleif: idle detect interrupt bit 1 = idle condition is detected (constant idle state of 3 ms or more) 0 = no idle condition is detected bit 3 trnif: token processing complete interrupt bit 1 = processing of the current token is complete; read the u1stat register for endpoint information 0 = processing of the current token not complete; clear the u1stat register or load the next token from u1stat bit 2 sofif: start-of-frame token interrupt bit 1 = a start-of-frame token received by the peripheral or the start-of-frame threshold reached by the host 0 = no start-of-frame token received or threshold reached bit 1 uerrif: usb error condition interrupt bit 1 = an unmasked error condition has occurred; only error states enabled in the u1eie register can set this bit 0 = no unmasked error condition has occurred bit 0 detachif: detach interrupt bit 1 = a peripheral detachment has been detected by the module; reset state must be cleared before this bit can be reasserted 0 = no peripheral detachment is detected. individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bit- wise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. note: individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
? 2010 microchip technology inc. ds39975a-page 263 pic24fj256gb210 family register 18-18: u1ie: usb interrupt enable register (all usb modes) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie (1) resumeie idleie trnie sofie uerrie urstie detachie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 attachie: peripheral attach interrupt bit (host mode only) (1) 1 = interrupt is enabled 0 = interrupt is disabled bit 5 resumeie: resume interrupt bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 idleie: idle detect interrupt bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 trnie: token processing complete interrupt bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 sofie: start-of-frame token interrupt bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 uerrie: usb error condition interrupt bit 1 = interrupt is enabled 0 = interrupt is disabled bit 0 urstie or detachie: usb reset interrupt (device mode) or usb detach interrupt (host mode) enable bit 1 = interrupt is enabled 0 = interrupt is disabled note 1: unimplemented in device mode, read as ? 0 ?.
pic24fj256gb210 family ds39975a-page 264 ? 2010 microchip technology inc. register 18-19: u1eir: usb error interrupt status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/k-0, hs u-0 r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs r/k-0, hs btsef ? dmaef btoef dfn8ef crc16ef crc5ef pidef eofef bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit k = write ?1? to clear bit hs = hardware settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = bit stuff error has been detected 0 = no bit stuff error has been detected bit 6 unimplemented: read as ? 0 ? bit 5 dmaef: dma error flag bit 1 = a usb dma error condition is detected ; t he data size indicated by the bd byte count field is less than the number of received bytes, the received data is truncated 0 = no dma error bit 4 btoef: bus turnaround time-out error flag bit 1 = bus turnaround time-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field was not an integral number of bytes 0 = data field was an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = crc16 failed 0 = crc16 passed bit 1 for device mode: crc5ef: crc5 host error flag bit 1 = token packet is rejected due to crc5 error 0 = token packet is accepted (no crc5 error) for host mode: eofef: end-of-frame error flag bit 1 = end-of-frame error has occurred 0 = end-of-frame interrupt is disabled bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed note: individual bits can only be cleared by writing a ? 1 ? to the bit position as part of a word write operation on the entire register. using boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.
? 2010 microchip technology inc. ds39975a-page 265 pic24fj256gb210 family register 18-20: u1eie: usb error interrupt enable register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee ? dmaee btoee dfn8ee crc16ee crc5ee pidee eofee bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 6 unimplemented: read as ? 0 ? bit 5 dmaee: dma error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 3 dfn8ee: data field size error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 1 for device mode: crc5ee: crc5 host error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled for host mode: eofee: end-of-frame error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 0 pidee: pid check failure interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled
pic24fj256gb210 family ds39975a-page 266 ? 2010 microchip technology inc. 18.7.3 usb endpoint management registers register 18-21: u1epn: usb endpoint n control registers (n = 0 to 15) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd (1) retrydis (1) ? epcondis eprxen eptxen epstall ephshk bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 lspd: low-speed direct connection enable bit (u1ep0 only) (1) 1 = direct connection to a low-speed device is enabled 0 = direct connection to a low-speed device is disabled bit 6 retrydis: retry disable bit (u1ep0 only) (1) 1 = retry nak transactions is disabled 0 = retry nak transactions is enabled; retry is done in hardware bit 5 unimplemented: read as ? 0 ? bit 4 epcondis: bidirectional endpoint control bit if eptxen and eprxen = 1 : 1 = disable endpoint n from control transfers; only tx and rx transfers are allowed 0 = enable endpoint n for control (setup) transfers; tx and rx transfers are also allowed for all other combinations of eptxen and eprxen: this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint n receive is enabled 0 = endpoint n receive is disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint n transmit is enabled 0 = endpoint n transmit is disabled bit 1 epstall: endpoint stall status bit 1 = endpoint n was stalled 0 = endpoint n was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake is enabled 0 = endpoint handshake is disabled (typically used for isochronous endpoints) note 1: these bits are available only for u1ep0 and only in host mode. for all other u1epn registers, these bits are always unimplemented and read as ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 267 pic24fj256gb210 family 18.7.4 usb v bus power control register register 18-22: u1pwmcon: usb v bus pwm generator control register r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 pwmen ? ? ? ? ? pwmpol cnten bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pwmen: pwm enable bit 1 = pwm generator is enabled 0 = pwm generator is disabled; output is held in the reset state specified by pwmpol bit 14-10 unimplemented: read as ? 0 ? bit 9 pwmpol: pwm polarity bit 1 = pwm output is active-low and resets high 0 = pwm output is active-high and resets low bit 8 cnten: pwm counter enable bit 1 = counter is enabled 0 = counter is disabled bit 7-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 268 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 269 pic24fj256gb210 family 19.0 enhanced parallel master port (epmp) the enhanced parallel master port (epmp) module provides a parallel 4-bit (master mode only), 8-bit (mas- ter and slave modes) or 16-bit (master mode only) data bus interface to communicate with off-chip modules, such as memories, fifos, lcd controllers and other microcontrollers. this module can serve as either the master or the slave on the communication bus. for epmp master modes, all external addresses are mapped into the internal extended data space (eds). this is done by allocating a region of the eds for each chip select, and then assigning each chip select to a particular external resource, such as a memory or external controller. this region should not be assigned to another device resource, such as ram or sfrs. to perform a write or read on an external resource, the cpu should simply perform a write or read within the address range assigned for epmp. key features of the epmp module are: ? extended data space (eds) interface allows direct access from the cpu ? up to 23 programmable address lines ? up to 2 chip select lines ? up to 2 acknowledgement lines (one per chip select) ? 4-bit, 8-bit or 16-bit wide data bus ? programmable strobe options (per chip select) - individual read and write strobes or; - read/write strobe with enable strobe ? programmable address/data multiplexing ? programmable address wait states ? programmable data wait states (per chip select) ? programmable polarity on control signals (per chip select) ? legacy parallel slave port support ? enhanced parallel slave support - address support - 4-byte deep auto-incrementing buffer 19.1 altpmp setting many of the lower order epmp address pins are shared with adc inputs. this is an untenable situation for users that need both the adc channels and the epmp bus. if the user does not need to use all the address bits, then by clearing the altpmp (cw3<12>) config- uration bit, the lower order address bits can be mapped to higher address pins, which frees the adc channels. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 42. ?enhanced parallel master port (epmp)? (ds39730). the informa- tion in this data sheet supersedes the information in the frm. note: the alternate pmp pin selection is not available in 64-pin devices (pic24fjxxxgb206) and so the configuration bit, altpmp, is also not available. table 19-1: alternate epmp pins (1) pin altpmp = 0 altpmp = 1 ra14 pmcs2 pma22 rc4 pma22 pmcs2 rf12 pma5 pma18 rg6 pma18 pma5 rg7 pma20 pma4 ra3 pma4 pma20 rg8 pma21 pma3 ra4 pma3 pma21 note 1: the alternate epmp pins are valid only for 100-pin devices (pic24fjxxxgb210).
pic24fj256gb210 family ds39975a-page 270 ? 2010 microchip technology inc. table 19-2: parallel master port pin description pin name type description pma<22:16> (1) o address bus bits<22-16> pma<15>, pmcs2 o address bus bit<15> o chip select 2 (alternate location) i/o data bus bit<15> when port size is 16 bits and address is multiplexed pma<14>, pmcs1 o address bus bit<14> o chip select 1 (alternate location) i/o data bus bit<14> when port size is 16-bit and address is multiplexed pma<13:8> o address bus bits<13-8> i/o data bus bits<13-8> when port size is 16 bits and address is multiplexed pma<7:3> o address bus bits<7-3> pma<2>, pmalu (1) o address bus bit<2> o address latch upper strobe for multiplexed address pma<1>, pmalh i/o address bus bit<1> o address latch high strobe for multiplexed address pma<0>, pmall i/o address bus bit<0> o address latch low strobe for multiplexed address pmd<15:8> i/o data bus bits<15-8> when address is not multiplexed pmd<7:4> i/o data bus bits<7-4> o address bus bits<7-4> when port size is 4 bits and address is multiplexed with 1 address phase pmd<3:0> i/o data bus bits<3-0> pmcs1 i/o chip select 1 pmcs2 o chip select 2 pmwr, pmenb i/o write strobe or enable signal depending on strobe mode pmrd, pmrd/pmwr i/o read strobe or read/write signal depending on strobe mode pmbe1 (1) o byte indicator pmbe0 o nibble or byte indicator pmack1 i acknowledgment 1 pmack2 i acknowledgment 2 note 1: available only in 100-pin devices (pic24fjxxxgb210).
? 2010 microchip technology inc. ds39975a-page 271 pic24fj256gb210 family register 19-1: pmcon1: ep mp control register 1 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 pmpen ? psidl adrmux1 adrmux0 ?mode1mode0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 csf1 csf0 alp almode ? buskeep irqm1 irqm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pmpen: parallel master port enable bit 1 = epmp is enabled 0 = epmp is disabled bit 14 unimplemented: read as ? 0 ? bit 13 psidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = lower address bits are multiplexed with data bits using 3 address phases 10 = lower address bits are multiplexed with data bits using 2 address phases 01 = lower address bits are multiplexed with data bits using 1 address phase 00 = address and data appear on separate pins bit 10 unimplemented: read as ? 0 ? bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 10 = enhanced psp; pins used are pmrd, pmwr, pmcs, pmd<7:0> and pma<1:0> 01 = buffered psp; pins used are pmrd, pmwr, pmcs and pmd<7:0> 00 = legacy parallel slave port; pmrd, pmwr, pmcs and pmd<7:0> pins are used bit 7-6 csf<1:0>: chip select function bits 11 = reserved 10 = pma<15> used for chip select 2, pma<14> used for chip select 1 01 = pma<15> used for chip select 2, pmcs1 used for chip select 1 00 = pmcs2 used for chip select 2, pmcs1 used for chip select 1 bit 5 alp: address latch polarity bit 1 = active-high (pmall, pmalh and pmalu) 0 = active-low (pmall , pmalh and pmalu ) bit 4 almode: address latch strobe mode bit 1 = enable ?smart? address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = disable ?smart? address strobes bit 3 unimplemented: read as ? 0 ? bit 2 buskeep: bus keeper bit 1 = data bus keeps its last value when not actively being driven 0 = data bus is in high-impedance state when not actively being driven bit 1-0 irqm<1:0>: interrupt request mode bits 11 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode), or on a read or write operation when pma<1:0> = 11 (addressable psp mode only) 10 = reserved 01 = interrupt generated at the end of a read/write cycle 00 = no interrupt is generated
pic24fj256gb210 family ds39975a-page 272 ? 2010 microchip technology inc. register 19-2: pmcon2: ep mp control register 2 r-0, hsc u-0 r/c-0, hs r/c-0, hs u-0 u-0 u-0 u-0 busy ? error timeout ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 raddr23 raddr22 raddr21 raddr20 raddr19 raddr18 raddr17 raddr16 bit 7 bit 0 legend: hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? c = clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 busy: busy bit (master mode only) 1 = port is busy 0 = port is not busy bit 14 unimplemented: read as ? 0 ? bit 13 error: error bit 1 = transaction error (illegal transaction was requested) 0 = transaction completed successfully bit 12 timeout: time-out bit 1 = transaction timed out 0 = transaction completed successfully bit 11-8 unimplemented: read as ? 0 ? bit 7-0 raddr<23:16>: parallel master port reserved address space bits (1) note 1: if raddr<23:16> = 00000000 , then the last eds address for chip select 2 will be 0xffffff.
? 2010 microchip technology inc. ds39975a-page 273 pic24fj256gb210 family register 19-3: pmcon3: ep mp control register 3 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ptwren ptrden ptbe1en ptbe0en ? awaitm1 awaitm0 awaite bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?pten22 (1) pten21 (1) pten20 (1) pten19 (1) pten18 (1) pten17 (1) pten16 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ptwren: write/enable strobe port enable bit 1 = pmwr/pmenb port is enabled 0 = pmwr/pmenb port is disabled bit 14 ptrden: read/write strobe port enable bit 1 =pmrd/pmwr port is enabled 0 =pmrd/pmwr port is disabled bit 13 ptbe1en: high nibble/byte enable port enable bit 1 = pmbe1 port is enabled 0 = pmbe1 port is disabled bit 12 ptbe0en: low nibble/byte enable port enable bit 1 = pmbe0 port is enabled 0 = pmbe0 port is disabled bit 11 unimplemented: read as ? 0 ? bit 10-9 awaitm<1:0>: address latch strobe wait states bits 11 = wait of 3? t cy 10 = wait of 2? t cy 01 = wait of 1? t cy 00 = wait of ? t cy bit bit 8 awaite: address hold after address latch strobe wait states bits 1 = wait of 1? t cy 0 = wait of ? t cy bit 7 unimplemented: read as ? 0 ? bit 6-0 pten<22:16>: epmp address port enable bits (1) 1 = pma<22:16> function as epmp address lines 0 = pma<22:16> function as port i/os note 1: not available on 64-pin devices (pic24fjxxxgb206).
pic24fj256gb210 family ds39975a-page 274 ? 2010 microchip technology inc. register 19-4: pmcon4: ep mp control register 4 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten15 pten14 pten13 pten12 pten11 pten10 pten9 pten8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten7 pten6 pten5 pten4 pten3 pten2 pten1 pten0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pten15: pma15 port enable bit 1 = pma15 functions as either address line 15 or chip select 2 0 = pma15 functions as port i/o bit 14 pten14: pma14 port enable bit 1 = pma14 functions as either address line 14 or chip select 1 0 = pma14 functions as port i/o bit 13-3 pten<13:3>: epmp address port enable bits 1 = pma<13:3> function as epmp address lines 0 = pma<13:3> function as port i/os bit 2-0 pten<2:0>: pmalu/pmalh/pmall strobe enable bits 1 = pma<2:0> function as either address lines or address latch strobes 0 = pma<2:0> function as port i/os
? 2010 microchip technology inc. ds39975a-page 275 pic24fj256gb210 family register 19-5: pmcsxcf: chip se lect x config uration register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 csdis csp cspten bep ? wrsp rdsp sm bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ackp ptsz1 ptsz0 ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 csdis: chip select x disable bit 1 = disable the chip select x functionality 0 = enable the chip select x functionality bit 14 csp: chip select x polarity bit 1 = active-high (pmcsx) 0 =active-low (pmcsx ) bit 13 cspten: pmcsx port enable bit 1 = pmcsx port is enabled 0 = pmcsx port is disabled bit 12 bep: chip select x nibble/byte enable polarity bit 1 = nibble/byte enable is active-high (pmbe0, pmbe1) 0 = nibble/byte enable is active-low (pmbe0 , pmbe1 ) bit 11 unimplemented: read as ? 0 ? bit 10 wrsp: chip select x write strobe polarity bit for slave modes and master mode when sm = 0 : 1 = write strobe is active-high (pmwr) 0 = write strobe is active-low (pmwr ) for master mode when sm = 1 : 1 = enable strobe is active-high (pmenb) 0 = enable strobe is active-low (pmenb ) bit 9 rdsp: chip select x read strobe polarity bit for slave modes and master mode when sm = 0 : 1 = read strobe is active-high (pmrd) 0 = read strobe is active-low (pmrd ) for master mode when sm = 1 : 1 = read/write strobe is active-high (pmrd/pmwr ) 0 = read/write strobe is active-low (pmrd /pmwr) bit 8 sm: chip select x strobe mode bit 1 = read/write and enable strobes (pmrd/pmwr and pmenb) 0 = read and write strobes (pmrd and pmwr) bit 7 ackp: chip select x acknowledge polarity bit 1 = ack is active-high (pmack1) 0 = ack is active-low (pmack1 ) bit 6-5 ptsz<1:0>: chip select x port size bits 11 =reserved 10 = 16-bit port size (pmd<15:0>) 01 = 4-bit port size (pmd<3:0>) 00 = 8-bit port size (pmd<7:0>) bit 4-0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 276 ? 2010 microchip technology inc. register 19-6: pmcsxbs: chip select x base address register r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) base23 base22 base21 base20 base19 base18 base17 base16 bit 15 bit 8 r/w (1) u-0 u-0 u-0 r/w (1) u-0 u-0 u-0 base15 ? ? ? base11 ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 base<23:15>: chip select x base address bits (2) bit 6-4 unimplemented: read as ? 0 ? bit 3 base<11>: chip select x base address bits (2) bit 2-0 unimplemented: read as ? 0 ? note 1: value at por is 0x0200 for pmcs1bs and 0x0600 for pmcs2bs. 2: if the whole pmcs2bs register is written together as 0x0000, then the last eds address for the chip select 1 will be 0xffffff. in this case, the chip select 2 should not be used. pmcs1bs has no such feature.
? 2010 microchip technology inc. ds39975a-page 277 pic24fj256gb210 family register 19-7: pmcsxmd: chip select x mode register r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ackm1 ackm0 ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dwaitb1 dwaitb0 dwaitm3 dwaitm2 dwaitm1 dwaitm0 dwaite1 dwaite0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 ackm<1:0>: chip select x acknowledge mode bits 11 = reserved 10 = pmackx is used to determine when a read/write operation is complete 01 = pmackx is used to determine when a read/write operation is complete with time-out if dwaitm<3:0> = 0000 , the maximum time-out is 255 t cy , else it is dwaitm<3:0> cycles. 00 = pmackx is not used bit 13-8 unimplemented: read as ? 0 ? bit 7-6 dwaitb<1:0>: chip select x data setup before read/write strobe wait states bits 11 = wait of 3? t cy 10 = wait of 2? t cy 01 = wait of 1? t cy 00 = wait of ? t cy bit 5-2 dwaitm<3:0>: chip select x data read/write strobe wait states bits for write operations: 1111 = wait of 15? t cy . . . 0001 = wait of 1? t cy 0000 = wait of ? t cy f or read operations: 1111 = wait of 15? t cy . . . 0001 = wait of 1? t cy 0000 = wait of ? t cy bit 1-0 dwaite<1:0>: chip select x data hold after read/write strobe wait states bits for write operations: 11 = wait of 3? t cy 10 = wait of 2? t cy 01 = wait of 1? t cy 00 = wait of ? t cy f or read operations: 11 = wait of 3 t cy 10 = wait of 2 t cy 01 = wait of 1 t cy 00 = wait of 0 t cy
pic24fj256gb210 family ds39975a-page 278 ? 2010 microchip technology inc. register 19-8: pmstat: epmp status register (slave mode only) r-0, hsc r/w-0 hs u-0 u-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc ibf ibov ? ? ib3f ib2f ib1f ib0f bit 15 bit 8 r-1, hsc r/w-0 hs u-0 u-0 r-1, hsc r-1, hsc r-1, hsc r-1, hsc obe obuf ? ? ob3e ob2e ob1e ob0e bit 7 bit 0 legend: hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input register occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ibxf: input buffer x status full bit (1) 1 = input buffer contains unread data (reading buffer will clear this bit) 0 = input buffer does not contain unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output register (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 obxe: output buffer x status empty bit 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains untransmitted data note 1: even though an individual bit represents the byte in the buffer, the bits corresponding to the word (byte 0 and 1, or byte 2 and 3) gets cleared even on byte reading.
? 2010 microchip technology inc. ds39975a-page 279 pic24fj256gb210 family register 19-9: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: epmp module ttl input buffer select bit 1 = epmp module inputs (pmdx, pmcs1) use ttl input buffers 0 = epmp module inputs use schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe (rcfgcal<10>) bit must also be set.
pic24fj256gb210 family ds39975a-page 280 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 281 pic24fj256gb210 family 20.0 real-time clock and calendar (rtcc) the real-time clock and calendar (rtcc) provides a function that can be calibrated. key features of the rtcc module are: ? operates in sleep mode ? provides hours, minutes and seconds using 24-hour format ? visibility of half of one second period ? provides calendar ? weekday, date, month and year ? alarm configurable for half a second, one second,10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat chime ? years, 2000 to 2099, leap year correction ? bcd format for smaller software overhead ? optimized for long-term battery operation ? user calibration of the 32.768 khz clock crystal/32k intrc frequency with periodic auto-adjust - calibration to within 2.64 seconds error per month - calibrates up to 260 ppm of crystal error figure 20-1: rtcc block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 29. ?real-time clock and calendar (rtcc)? (ds39696). the information in this data sheet supersedes the information in the frm. rtcc prescalers rtcc timer comparator compare registers repeat counter year mthdy wkdyhr minsec almthdy alwdhr alminsec with masks rtcc interrupt logic rcfgcal alcfgrpt alarm event 32.768 khz input from sosc 0.5s rtcc clock domain alarm pulse rtcc interrupt cpu clock domain rtcval alrmval rtcc pin rtcoe
pic24fj256gb210 family ds39975a-page 282 ? 2010 microchip technology inc. 20.1 rtcc module registers the rtcc module registers are organized into three categories: ? rtcc control registers ? rtcc value registers ? alarm value registers 20.1.1 register mapping to limit the register interface, the rtcc timer and alarm time registers are accessed through the corre- sponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rcfgcal<9:8>) to select the desired timer register pair (see table 20-1). by writing the rtcvalh byte, the rtcc pointer value, rtcptr<1:0> bits, decrement by one until they reach ? 00 ?. once they reach ? 00 ?, the minutes and seconds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 20-1: rtcval register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alcfgrpt<9:8>) to select the desired alarm register pair (see table 20-2). by writing the alrmvalh byte, the alarm pointer value bits, alrmptr<1:0>, decrement by one until they reach ? 00 ?. once they reach ? 00 ?, the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. table 20-2: alrmval register mapping considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the alrmvalh or alrmvall bytes, they will decrement the alrmptr<1:0> value. the same applies to the rtcvalh or rtcvall bytes with the rtcptr<1:0> being decremented. 20.1.2 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren (rcfgcal<13>) bit must be set (refer to example 20-1). example 20-1: setting the rtcwren bit rtcptr <1:0> rtcc value register window rtcval<15:8> rtcval<7:0> 00 minutes seconds 01 weekday hours 10 month day 11 ? year alrmptr <1:0> alarm value register window alrmval<15:8> alrmval<7:0> 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 ?? note: this only applies to read operations and not write operations. note: to avoid accidental writes to the timer, it is recommended that the rtcwren bit (rcfgcal<13>) is kept clear at any other time. for the rtcwren bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of rtcwren; therefore, it is recommended that code follow the procedure in example 20-1. for applications written in c, the unlock sequence should be implemented using in-line assembly. asm volatile("disi #5"); asm volatile("mov #0x55, w7"); asm volatile("mov w7, _nvmkey"); asm volatile("mov #0xaa, w8"); asm volatile("mov w8, _nvmkey"); asm volatile("bset _rcfgcal, #13"); //set the rtcwren bit
? 2010 microchip technology inc. ds39975a-page 283 pic24fj256gb210 family 20.1.3 rtcc control registers register 20-1: rcfgcal: rtcc cali bration and config uration register (1) r/w-0 u-0 r/w-0 r-0, hsc r-0, hsc r/w-0 r/w-0, hsc r/w-0, hsc rtcen (2) ? rtcwren rtcsync halfsec (3) rtcoe rtcptr1 rtcptr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall registers can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 12 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alcfgrpt registers can change while reading due to a rollover ripple resulting in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall or alcfgrpt registers can be read without concern over a rollover ripple bit 11 halfsec: half-second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output is enabled 0 = rtcc output is disabled bit 9-8 rtcptr<1:0>: rtcc value register window pointer bits points to the corresponding rtcc value register s when reading the rtcvalh and rtcvall registers. the rtcptr<1:0> value decrements on every read or write of rtcvalh until it reaches ? 00 ?. rtcval<15:8>: 11 = reserved 10 =month 01 = weekday 00 = minutes rtcval<7:0>: 11 =year 10 =day 01 = hours 00 = seconds note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to ? 0 ? on a write to the lower half of the minsec register.
pic24fj256gb210 family ds39975a-page 284 ? 2010 microchip technology inc. bit 7-0 cal<7:0>: rtc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every one minute . . . 11111111 = minimum negative adjustment; subtracts 4 rtc clock pulses every one minute 00000001 = minimum positive adjustment; adds 4 rtc clock pulses every one minute 00000000 = no adjustment . . . 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every one minute register 20-1: rcfgcal: rtcc cali bration and config uration register (1) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to ? 0 ? on a write to the lower half of the minsec register. register 20-2: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: epmp module ttl input buffer select bit 1 = epmp module inputs (pmdx, pmcs1) use ttl input buffers 0 = epmp module inputs use schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe (rcfgcal<10>) bit must also be set.
? 2010 microchip technology inc. ds39975a-page 285 pic24fj256gb210 family register 20-3: alcfgrpt: al arm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0, hsc r/w-0, hsc alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 bit 15 bit 8 r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 00h and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 00h to ffh 0 = chime is disabled; arpt<7:0> bits stop once they reach 00h bit 13-10 amask<3:0>: alarm mask configuration bits 11xx = reserved ? do not use 101x = reserved ? do not use 1001 = once a year (except when configured for february 29 th , once every 4 years) 1000 = once a month 0111 = once a week 0110 = once a day 0101 = every hour 0100 = every 10 minutes 0011 = every minute 0010 = every 10 seconds 0001 = every second 0000 = every half second bit 9-8 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value registers when reading the alrmvalh and alrmvall registers. the alrmptr<1:0> value decrements on every read or write of alrmvalh until it reaches ? 00 ?. alrmval<15:8>: 11 = unimplemented 10 =alrmmnth 01 =alrmwd 00 = alrmmin alrmval<7:0>: 11 = unimplemented 10 =alrmday 01 =alrmhr 00 = alrmsec bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times ... 00000000 = alarm will not repeat the counter decrements on any alarm event. the counter is prevented from rolling over from 00h to ffh unless chime = 1 .
pic24fj256gb210 family ds39975a-page 286 ? 2010 microchip technology inc. 20.1.4 rtcval register mappings register 20-4: year: year value register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc yrten3 yrten2 yrten1 yrten0 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 yrten<3:0>: binary coded decimal value of year?s tens digit bits contains a value from 0 to 9. bit 3-0 yrone<3:0>: binary coded decimal value of year?s ones digit bits contains a value from 0 to 9. note 1: a write to the year register is only allowed when rtcwren = 1 . register 20-5: mthdy: month and day value register (1) u-0 u-0 u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of 0 or 1. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
? 2010 microchip technology inc. ds39975a-page 287 pic24fj256gb210 family register 20-6: wkdyhr: weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 20-7: minsec: minutes and seconds value register u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc r/w-x, hsc ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
pic24fj256gb210 family ds39975a-page 288 ? 2010 microchip technology inc. 20.1.5 alrmval register mappings register 20-8: almthdy: alarm month and day value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of 0 or 1. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
? 2010 microchip technology inc. ds39975a-page 289 pic24fj256gb210 family register 20-9: alwdhr: alarm weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 20-10: alminsec: alarm minut es and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
pic24fj256gb210 family ds39975a-page 290 ? 2010 microchip technology inc. 20.2 calibration the real-time crystal input can be calibrated using the periodic auto-adjust feature. when properly calibrated, the rtcc can provide an error of less than 3 seconds per month. this is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the rcfgcal register. the 8-bit signed value loaded into the lower half of rcfgcal is multiplied by four and will either be added or subtracted from the rtcc timer, once every minute. refer to the following steps for rtcc calibration: 1. using another timer resource on the device, the user must find the error of the 32.768 khz crystal. 2. once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the rcfgcal register. equation 20-1: rtcc calibration 3. a) if the oscillator is faster then ideal (negative result form step 2), the rcfgcal register value needs to be negative. this causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) if the oscillator is slower then ideal (positive result from step 2), the rcfgcal register value needs to be positive. this causes the specified number of clock pulses to be added to the timer counter, once every minute. 4. divide the number of error clocks per minute by 4 to get the correct cal value and load the rcfgcal register with the correct value. (each 1-bit increment in cal adds or subtracts 4 pulses). writes to the lower half of the rcfgcal register should only occur when the timer is turned off or immediately after the rising edge of the seconds pulse. 20.3 alarm ? configurable from half second to one year ? enabled using the alrmen bit (alcfgrpt<15>, register 20-3) ? one-time alarm and repeat alarm options available 20.3.1 configuring the alarm the alarm feature is enabled using the alrmen bit. this bit is cleared when an alarm is issued. writes to alrmval should only take place when alrmen = 0 . as shown in figure 20-2, the interval selection of the alarm is configured through the amask bits (alcfgrpt<13:10>). these bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. the alarm can also be configured to repeat based on a preconfigured interval. the amount of times this occurs, once the alarm is enabled, is stored in the arpt bits, arpt<7:0> (alcfgrpt<7:0>). when the value of the arpt bits equals 00h and the chime bit (alcfgrpt<14>) is cleared, the repeat function is disabled and only a single alarm will occur. the alarm can be repeated up to 255 times by loading arpt<7:0> with ffh. after each alarm is issued, the value of the arpt bits is decremented by one. once the value has reached 00h, the alarm will be issued one last time, after which the alrmen bit will be cleared automatically and the alarm will turn off. indefinite repetition of the alarm can occur if the chime bit = 1 . instead of the alarm being disabled when the value of the arpt bits reaches 00h, it rolls over to ffh and continues counting indefinitely while chime is set. 20.3.2 alarm interrupt at every alarm event, an interrupt is generated. in addi- tion, an alarm pulse output is provided that operates at half the frequency of the alarm. this output is completely synchronous to the rtcc clock and can be used as a trigger clock to other peripherals. note: it is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. error (clocks per minute) = (ideal frequency? ? measured frequency) x 60 ?ideal frequency = 32,768h note: changing any of the registers, other then the rcfgcal and alcfgrpt registers and the chime bit while the alarm is enabled (alrmen = 1 ), can result in a false alarm event leading to a false alarm interrupt. to avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (alrmen = 0 ). it is recommended that the alcfgrpt register and chime bit be changed when rtcsync = 0 .
? 2010 microchip technology inc. ds39975a-page 291 pic24fj256gb210 family figure 20-2: alarm mask settings note 1: annually, except when c onfigured for february 29. s ss mss mm s s hh mm ss dhhmmss dd hh mm s s mm d d h h mm s s day of the week month day hours minutes seconds alarm mask setting (amask<3:0>) 0000 ? every half second 0001 ? every second 0010 ? every 10 seconds 0011 ? every minute 0100 ? every 10 minutes 0101 ? every hour 0110 ? every day 0111 ? every week 1000 ? every month 1001 ? every year (1)
pic24fj256gb210 family ds39975a-page 292 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 293 pic24fj256gb210 family 21.0 32-bit programmable cyclic redundancy check (crc) generator the 32-bit programmable crc generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. it offers the following features: ? user-programmable crc polynomial equation, up to 32 bits ? programmable shift direction (little or big-endian) ? independent data and polynomial lengths ? configurable interrupt output ? data fifo figure 21-1 displays a simplified block diagram of the crc generator. a simple version of the crc shift engine is displayed in figure 21-2. figure 21-1: crc block diagram figure 21-2: crc shift engine detail note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 41. ?32-bit programmable cyclic redundancy check (crc)? (ds39729). the information in this data sheet supersedes the information in the frm. crc interrupt variable fifo (4x32, 8x16 or 16x8) crcdath crcdatl shift buffer crc shift engine crcwdath crcwdatl shifter clock 2 * f cy lendian 1 0 crcisel 1 0 fifo empty event shift complete event note 1: n = plen<4:1> + 1. crc shift engine crcwdath crcwdatl bit 0 bit 1 bit n (1) x0 x1 xn (1) read/write bus shift buffer data
pic24fj256gb210 family ds39975a-page 294 ? 2010 microchip technology inc. 21.1 user interface 21.1.1 polynomial interface the crc module can be programmed for crc polynomials of up of up the 32 nd order, using up to 32 bits. polynomial length, which reflects the highest exponent in the equation, is selected by the plen<4:0> bits (crccon2<4:0>). the crcxorl and crcxorh registers control which exponent terms are included in the equation. setting a particular bit includes that exponent term in the equa- tion; functionally, this includes an xor operation on the corresponding bit in the crc engine. clearing the bit disables the xor. for example, consider two crc polynomials, one a 16-bit and the other a 32-bit equation. equation 21-1: 16-bit, 32-bit crc polynomials to program these polynomials into the crc generator, set the register bits as shown in table 21-1. note that the appropriate positions are set to ? 1 ? to indi- cate they are used in the equation (for example, x26 and x23). the ? 0 ? bit required by the equation is always xored; thus, x0 is a don?t care. for a polynomial of length 32, it is assumed that the 32 nd bit will be used. therefore, the x<31:1> bits do not have the 32 nd bit. 21.1.2 data interface the module incorporates a fifo that works with a vari- able data width. input data width can be configured to any value between one and 32 bits using the dwidth<4:0> bits (crccon2<12:8>). when the data width is greater than 15, the fifo is four words deep. when the dwitdh bits are between 15 and 8, the fifo is 8 words deep. when the dwidth bits are less than 8, the fifo is 16 words deep. the data for which the crc is to be calculated must first be written into the fifo. even if the data width is less than 8, the smallest data element that can be writ- ten into the fifo is one byte. for example, if dwidth is five, then the size of the data is dwidth + 1 or six. the data is written as a whole byte; the two unused upper bits are ignored by the module. once data is written into the msb of the crcdat reg- isters (that is, msb as defined by the data width), the value of the vword<4:0> bits (crccon1<12:8>) increments by one. for example, if dwidth is 24, the vword bits will increment when bit 7 of crcdath is written. therefore, crcdatl must always be written to before crcdath. the crc engine starts shifting data when the crcgo bit is set and the value of vword is greater than zero. each word is copied out of the fifo into a buffer regis- ter, which decrements vword. the data is then shifted out of the buffer. the crc engine continues shifting at a rate of two bits per instruction cycle, until vword reaches zero. this means that for a given data width, it takes half that number of instructions for each word to complete the calculation. for example, it takes 16 cycles to calculate the crc for a single word of 32-bit data. when vword reaches the maximum value for the configured value of dwidth (4, 8 or 16), the crcful bit becomes set. when vword reaches zero, the crcmpt bit becomes set. the fifo is emptied and the vword<4:0> bits are set to ? 00000 ? whenever crcen is ? 0 ?. at least one instruction cycle must pass after a write to crcwdat before a read of the vword bits is done. and x32+x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 x16 + x12 + x5 + 1 table 21-1: crc setup examples for 16 and 32-bit polynomials crc control bits bit values 16-bit polynomial 32-bit polynomial plen<4:0> 01111 11111 x<31:16> 0000 0000 0000 0001 0000 0100 1100 0001 x<15:0> 0001 0000 0010 000x 0001 1101 1011 011x
? 2010 microchip technology inc. ds39975a-page 295 pic24fj256gb210 family 21.1.3 data shift direction the lendian bit (crccon1<3>) is used to control the shift direction. by default, the crc will shift data through the engine, msb first. setting lendian (= 1 ) causes the crc to shift data, lsb first. this setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. note that this only changes the direction the data is shifted into the engine. the result of the crc calculation will still be a normal crc result, not a reverse crc result. 21.1.4 interrupt operation the module generates an interrupt that is configurable by the user for either of two conditions. if crcisel is ? 0 ?, an interrupt is generated when the vword<4:0> bits make a transition from a value of ? 1 ? to ? 0 ?. if crcisel is ? 1 ?, an interrupt will be generated after the crc operation finishes and the module sets the crcgo bit to ? 0 ?. manually setting crcgo to ? 0 ? will not generate an interrupt. note that when an interrupt occurs, the crc calculation would not yet be complete. the module will still need (plen + 1)/2 clock cycles after the interrupt is generated until the crc calculation is finished. 21.1.5 typical operation to use the module for a typical crc calculation: 1. set the crcen bit to enable the module. 2. configure the module for desired operation: a) program the desired polynomial using the crcxorl and crcxorh registers, and the plen<4:0> bits. b) configure the data width and shift direction using the dwidth and lendian bits. c) select the desired interrupt mode using the crcisel bit. 3. preload the fifo by writing to the crcdatl and crcdath registers until the crcful bit is set or no data is left. 4. clear old results by writing 00h to crcwdatl and crcwdath. the crcwdat registers can also be left unchanged to resume a previously halted calculation. 5. set the crcgo bit to start calculation. 6. write remaining data into the fifo as space becomes available. 7. when the calculation completes, crcgo is automatically cleared. an interrupt will be generated if crcisel = 1 . 8. read crcwdatl and crcwdath for the result of the calculation. there are eight registers used to control programmable crc operation: ? crccon1 ? crccon2 ? crcxorl ? crcxorh ? crcdatl ? crcdath ? crcwdatl ? crcwdath the crccon1 and crccon2 registers (register 21-1 and register 21-2) control the operation of the module and configure the various settings. the crcxor registers (register 21-3 and register 21-4) select the polynomial terms to be used in the crc equation. the crcdat and crcwdat registers are each register pairs that serve as buffers for the double-word input data, and crc processed output, respectively.
pic24fj256gb210 family ds39975a-page 296 ? 2010 microchip technology inc. register 21-1: crccon1: crc control 1 register r/w-0 u-0 r/w-0 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc crcen ? csidl vword4 vword3 vword2 vword1 vword0 bit 15 bit 8 r-0, hsc r-1, hsc r/w-0 r/w-0, hc r/w-0 u-0 u-0 u-0 crcful crcmpt crcisel crcgo lendian ? ? ? bit 7 bit 0 legend: hc = hardware clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 crcen: crc enable bit 1 = enables module 0 = disables module; all state machines, pointers and crcwdat/crcdath reset; other sfrs are not reset bit 14 unimplemented: read as ? 0 ? bit 13 csidl: crc stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 vword<4:0>: pointer value bits indicates the number of valid words in the fifo. has a maximum value of 8 when plen<4:0> ? 7 or 16 when plen<4:0> ? ? 7. bit 7 crcful: fifo full bit 1 = fifo is full 0 = fifo is not full bit 6 crcmpt: fifo empty bit 1 = fifo is empty 0 = fifo is not empty bit 5 crcisel: crc interrupt selection bit 1 = interrupt on fifo is empty; the final word of data is still shifting through the crc 0 = interrupt on shift is complete and results are ready bit 4 crcgo: start crc bit 1 = start crc serial shifter 0 = crc serial shifter is turned off bit 3 lendian: data shift direction select bit 1 = data word is shifted into the crc, starting with the lsb (little endian) 0 = data word is shifted into the crc, starting with the msb (big endian) bit 2-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 297 pic24fj256gb210 family register 21-2: crccon2: c rc control 2 register u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dwidth4 dwidth3 dwidth2 dwidth1 dwidth0 bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen4 plen3 plen2 plen1 plen0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 dwidth<4:0>: data word width configuration bits configures the width of the data word (data word width ? 1). bit 7-5 unimplemented: read as ? 0 ? bit 4-0 plen<4:0>: polynomial length configuration bits configures the length of the polynomial (polynomial length ? 1). register 21-3: crcxorl: crc xor polynomial register, low byte r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x15 x14 x13 x12 x11 x10 x9 x8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 x7 x6 x5 x4 x3 x2 x1 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 x<15:1>: xor of polynomial term x n enable bits bit 0 unimplemented: read as ? 0 ?
pic24fj256gb210 family ds39975a-page 298 ? 2010 microchip technology inc. register 21-4: crcxorh: crc xor high register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x31 x30 x29 x28 x27 x26 x25 x24 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x23 x22 x21 x20 x19 x18 x17 x16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 x<31:16>: xor of polynomial term x n enable bits register 21-5: crcdatl: crc data low register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data15 data14 data13 data12 data11 data10 data9 data8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data7 data6 data5 data4 data3 data2 data1 data0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 data<15:0>: crc input data bits writing to this register fills the fifo; reading from this register returns ? 0 ?. register 21-6: crcdath: crc data high register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data15 data14 data13 data12 data11 data10 data9 data8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 data7 data6 data5 data4 data3 data2 data1 data0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 data<15:0>: crc input data bits writing to this register fills the fifo; reading from this register returns ? 0 ?.
? 2010 microchip technology inc. ds39975a-page 299 pic24fj256gb210 family register 21-7: crcwdatl: crc shift low register r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc sdata15 sdata14 sdata13 sdata12 sdata11 sdata10 sdata9 sdata8 bit 15 bit 8 r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc sdata7 sdata6 sdata5 sdata4 sdata3 sdata2 sdata1 sdata0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sdata<15:0>: crc shift register bits writing to this register writes to the crc shift register through the crc write bus. reading from this register reads the crc read bus. register 21-8: crcwdath: crc shift high register r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc sdata31 sdata30 sdata29 sdata28 sdata27 sdata26 sdata25 sdata24 bit 15 bit 8 r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc sdata23 sdata22 sdata21 sdata20 sdata19 sdata18 sdata17 sdata16 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 sdata<31:16>: crc input data bits writing to this register writes to the crc shift register through the crc write bus. reading from this register reads the crc read bus.
pic24fj256gb210 family ds39975a-page 300 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 301 pic24fj256gb210 family 22.0 10-bit high-speed a/d converter the 10-bit a/d converter has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 500 ksps ? 24 analog input pins (pic24fjxxxgbx10 devices) and 16 analog input pins (pic24fjxxxgbx06 devices) ? external voltage reference input pins ? internal band gap reference inputs ? automatic channel scan mode ? selectable conversion trigger source ? 32-word conversion result buffer ? selectable buffer fill modes ? four result alignment options ? operation during cpu sleep and idle modes on all pic24fj256gb210 family devices, the 10-bit a/d converter has 24 analog input pins, designated an0 through an23. in addition, there are two analog input pins for external voltage reference connections (v ref + and v ref -). these voltage reference inputs may be shared with other analog input pins. a block diagram of the a/d converter is shown in figure 22-1. to perform an a/d conversion: 1. configure the a/d module: a) configure the port pins as analog inputs and/or select band gap reference inputs (ancfg registers). b) select the voltage reference source to match the expected range on analog inputs (ad1con2<15:13>). c) select the analog conversion clock to match the desired data rate with the processor clock (ad1con3<7:0>). d) select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>). e) select how the conversion results are presented in the buffer (ad1con1<9:8>). f) select the interrupt rate (ad1con2<6:2>). g) turn on the a/d module (ad1con1<15>). 2. configure the a/d interrupt (if required): a) clear the ad1if bit. b) select the a/d interrupt priority. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 17. ?10-bit a/d converter? (ds39705). the information in this data sheet supersedes the information in the frm.
pic24fj256gb210 family ds39975a-page 302 ? 2010 microchip technology inc. figure 22-1: 10-bit high-speed a/d converter block diagram comparator 10-bit sar conversion logic v ref + dac an23 an0 an1 an2 v ref - sample control s/h av ss av dd ad1buf0: ad1buf1f ad1con1 ad1con2 ad1con3 ad1chs ancfg control logic data formatting input mux control conversion control pin config control internal data bus 16 v r + v r - mux a mux b v inh v inl v inh v inh v inl v inl v r + v r - v r select v bg v bg /2 ad1cssl ad1cssh v bg /6 v cap
? 2010 microchip technology inc. ds39975a-page 303 pic24fj256gb210 family register 22-1: ad1con1: a/d control register 1 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 adon (1) ?adsidl ? ? ?form1form0 bit 15 bit 8 r/w -0 r/w -0 r/w-0 u-0 u-0 r/w-0 r -0, hsc r -0, hsc ssrc2 ssrc1 ssrc0 ? ? asam samp done bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: a/d operating mode bit (1) 1 = a/d converter module is operating 0 = a/d converter is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9-8 form<1:0>: data output format bits 11 = signed fractional ( sddd dddd dd00 0000 ) 10 = fractional ( dddd dddd dd00 0000 ) 01 = signed integer ( ssss sssd dddd dddd ) 00 = integer ( 0000 00dd dddd dddd ) bit 7-5 ssrc<2:0>: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto-convert) 110 = ctmu event ends sampling and starts conversion 101 = reserved 100 = timer5 compare ends sampling and starts conversion 011 = reserved 010 = timer3 compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion bit 4-3 unimplemented: read as ? 0 ? bit 2 asam: a/d sample auto-start bit 1 = sampling begins immediately after the last conversion completes; the samp bit is auto-set. 0 = sampling begins when the samp bit is set bit 1 samp: a/d sample enable bit 1 = a/d sample/hold amplifier is sampling input 0 = a/d sample/hold amplifier is holding bit 0 done: a/d conversion status bit 1 = a/d conversion is done 0 = a/d conversion is not done note 1: the values of the adc1bufx registers will not retain their values once the adon bit is cleared. read out the conversion values from the buffer before disabling the module.
pic24fj256gb210 family ds39975a-page 304 ? 2010 microchip technology inc. register 22-2: ad1con2: a/d control register 2 r/w-0 r/w-0 r/w-0 r-0 u-0 r/w-0 u-0 u-0 vcfg2 vcfg1 vcfg0 r ? cscna ? ? bit 15 bit 8 r-0, hsc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs smpi4 smpi3 smpi2 smpi1 smpi0 bufm alts bit 7 bit 0 legend: r = reserved bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: voltage reference configuration bits bit 12 reserved: maintain as ? 0 ? bit 11 unimplemented: read as ? 0 ? bit 10 cscna: scan input selections for the ch0+ s/h input for mux a input multiplexer setting bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit (valid only when bufm = 1 ) 1 = a/d is currently filling buffer, 10-1f, user should access data in 00-0f 0 = a/d is currently filling buffer, 00-0f, user should access data in 10-1f bit 6-2 smpi<4:0>: sample/convert sequences per interrupt selection bits 11111 = interrupts at the completion of conversion for each 32 nd sample/convert sequence 11110 = interrupts at the completion of conversion for each 31 st sample/convert sequence . . . 00001 = interrupts at the completion of conversion for each 2 nd sample/convert sequence 00000 = interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: buffer mode select bit 1 = buffer is configured as two 16-word buffers (adc1bufn<31:16> and adc1bufn<15:0>) 0 = buffer is configured as one 32-word buffer (adc1bufn<31:0>) bit 0 alts: alternate input sample mode select bit 1 = uses mux a input multiplexer settings for the first sample, then alternates between mux b and mux a input multiplexer settings for all subsequent samples 0 = always uses the mux a input multiplexer settings vcfg<2:0> v r +v r - 000 av dd av ss 001 external v ref + pin av ss 010 av dd external v ref - pin 011 external v ref + pin external v ref - pin 1xx av dd av ss
? 2010 microchip technology inc. ds39975a-page 305 pic24fj256gb210 family register 22-3: ad1con3: a/d control register 3 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc r r samc4 samc3 samc2 samc1 samc0 bit 15 bit 8 r/w -0 r/w -0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: a/d conversion clock source bit 1 = a/d internal rc clock 0 = clock is derived from the system clock bit 14-13 reserved : maintain as ? 0 ? bit 12-8 samc<4:0>: auto-sample time bits 11111 = 31 t ad . . . 00001 = 1 t ad 00000 = 0 t ad (not recommended) bit 7-0 adcs<7:0>: a/d conversion clock select bits 11111111 = 256 * t cy 00000001 = 2 * t cy 00000000 = t cy
pic24fj256gb210 family ds39975a-page 306 ? 2010 microchip technology inc. register 22-4: ad1chs: a/d input select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb4 (1) ch0sb3 (1) ch0sb2 (1) ch0sb1 (1) ch0sb0 (1) bit 15 bit 8 r/w -0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa4 (1) ch0sa3 (1) ch0sa2 (1) ch0sa1 (1) ch0sa0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for mux b multiplexer setting bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 14-13 unimplemented: read as ? 0 ? bit 12-8 ch0sb<4:0>: channel 0 positive input select for mux b (1) other = not available; do not use 11111 = no channel used; all inputs are floating; used for ctmu 11011 = channel 0 positive input is the band gap divided-by-six reference (v bg /6) 11010 = channel 0 positive input is the core voltage (v cap ) 11001 = channel 0 positive input is the band gap reference (v bg ) 11000 = channel 0 positive input is the band gap divided-by-two reference (v bg /2) 10111 = channel 0 positive input is an23 (2) . . . 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 7 ch0na: channel 0 negative input select for mux a multiplexer setting bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v r - bit 6-5 unimplemented: read as ? 0 ? bit 4-0 ch0sa<4:0>: channel 0 positive input select for mux (1) other = not available; do not use 11111 = no channel used; all inputs are floating; used for ctmu 11011 = channel 0 positive input is the band gap divided-by-six reference (v bg /6) 11010 = channel 0 positive input is the core voltage (v cap ) 11001 = channel 0 positive input is the band gap reference (v bg ) 11000 = channel 0 positive input is the band gap divided-by-two reference (v bg /2) 10111 = channel 0 positive input is an23 (2) . . . 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 note 1: combinations not shown here ( 11100 to 11110 ) are unimplemented; do not use. 2: channel 0 positive inputs, an16 through an23, ar e not available on 64-pin devices (pic24fjxxxgb206).
? 2010 microchip technology inc. ds39975a-page 307 pic24fj256gb210 family register 22-5: ancfg: a/d band gap reference configuration register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? vbg6en vbg2en vbgen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2 vbg6en: a/d input v bg /6 enable bit 1 = band gap voltage divided-by-six reference (v bg /6) is enabled 0 = band gap divided-by-six reference (v bg /6) is disabled bit 1 vbg2en: a/d input v bg /2 enable bit 1 = band gap voltage divided-by-two reference (v bg /2) is enabled 0 = band gap divided-by-two reference (v bg /2) is disabled bit 0 vbgen: a/d input v bg enable bit 1 = band gap voltage reference (v bg ) is enabled 0 = band gap reference (v bg ) is disabled register 22-6: ad1cssl: a/d input scan select register (low) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 bit 15 bit 8 r/w -0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 cssl<15:0>: a/d input pin scan selection bits 1 = corresponding analog channel is selected for input scan 0 = analog channel is omitted from input scan
pic24fj256gb210 family ds39975a-page 308 ? 2010 microchip technology inc. equation 22-1: a/d conversion clock period (1) register 22-7: ad1cssh: a/d input scan select register (high) u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? cssl27 cssl26 cssl25 cssl24 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl23 (1) cssl22 (1) cssl21 (1) cssl20 (1) cssl19 (1) cssl18 (1) cssl17 (1) cssl16 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11 cssl27: a/d input band gap scan selection bit 1 = band gap divided-by-six reference (v bg /6) is selected for input scan 0 = analog channel is omitted from input scan bit 10 cssl26: a/d input band gap scan selection bit 1 = internal core voltage (v cap ) is selected for input scan 0 = analog channel is omitted from input scan bit 9 cssl25: a/d input half band gap scan selection bit 1 = band gap reference (v bg ) is selected for input scan 0 = analog channel is omitted from input scan bit 8 cssl24: a/d input band gap scan selection bit 1 = band gap divided-by-two reference (v bg /2) is selected for input scan 0 = analog channel is omitted from input scan bit 7-0 cssl<23:16>: analog input pin scan selection bits (1) 1 = corresponding analog channel is selected for input scan 0 = analog channel is omitted from input scan note 1: unimplemented in 64-pin devices, read as ? 0 ?. note 1: based on t cy = 2 * t osc ; doze mode and pll are disabled. adcs = t ad t cy ? 1 t ad = t cy ? (adcs = 1)
? 2010 microchip technology inc. ds39975a-page 309 pic24fj256gb210 family figure 22-2: 10-bit a/d converter analog input model figure 22-3: a/d transfer function c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic ? 250 ? sampling switch r ss c hold = dac capacitance v ss v dd = 4.4 pf (typical) ? 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample/hold capacitance (from dac) various junctions note: c pin value depends on the device package and is not tested. the effect of c pin is negligible if rs ? 5 k ? . r ss ? 5 k ?? (typical) 6-11 pf (typical) 10 0000 0001 (513) 10 0000 0010 (514) 10 0000 0011 (515) 01 1111 1101 (509) 01 1111 1110 (510) 01 1111 1111 (511) 11 1111 1110 (1022) 11 1111 1111 (1023) 00 0000 0000 (0) 00 0000 0001 (1) output code 10 0000 0000 (512) (v inh ? v inl ) v r - v r + ? v r - 1024 512*(v r + ? v r -) 1024 v r + v r - + v r - + 1023*(v r + ? v r -) 1024 v r - + 0 (binary (decimal)) voltage level
pic24fj256gb210 family ds39975a-page 310 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 311 pic24fj256gb210 family 23.0 triple comparator module the triple comparator module provides three dual input comparators. the inputs to the comparator can be configured to use any one of five external analog inputs (cxina, cxinb, cxinc, cxind and v ref +) and a voltage reference input from one of the internal band gap references or the comparator voltage reference generator (v bg, v bg /2, v bg/6 and cv ref ). the comparator outputs may be directly connected to the cxout pins. when the respective coe equals ? 1 ?, the i/o pad logic makes the unsynchronized output of the comparator available on the pin. a simplified block diagram of the module in shown in figure 23-1. diagrams of the possible individual comparator configurations are shown in figure 23-2. each comparator has its own control register, cmxcon (register 23-1), for enabling and configuring its operation. the output and event status of all three comparators is provided in the cmstat register (register 23-2). figure 23-1: triple comp arator module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ? pic24f family reference manual ?. c1 v in - v in + c x inb c x inc c x ina c x ind cv ref v bg c2 v in - v in + c3 v in - v in + coe c1out pin cpol trigger/interrupt logic cevt evpol<1:0> cout input select logic cch<1:0> cref coe c2out pin cpol trigger/interrupt logic cevt evpol<1:0> cout coe c3out pin cpol trigger/interrupt logic cevt evpol<1:0> cout v bg /2 v bg /6 v ref + cvrefm<1:0> (1) v ref + cvrefp (1) + 01 00 10 11 01 00 10 11 1 0 0 1 note 1: refer register 24-1 for bit details.
pic24fj256gb210 family ds39975a-page 312 ? 2010 microchip technology inc. figure 23-2: individual comparator configurations when cref = 0 cx v in - v in + off (read as ? 0 ?) comparator off cen = 0 , cref = x , cch<1:0> = xx comparator cxinb > cxina compare cen = 1 , cch<1:0> = 00 coe cxout cx v in - v in + coe c x inb c x ina comparator cxind > cxina compare cen = 1 , cch<1:0> = 10 cx v in - v in + coe cxout c x ind c x ina comparator cxinc > cxina compare cx v in - v in + coe c x inc c x ina comparator v bg > cxina compare cx v in - v in + coe v bg c x ina pin pin cxout pin cxout pin cxout pin comparator v bg > cxina compare cen = 1 , cch<1:0> = 11 cx v in - v in + coe v bg /2 c x ina cxout pin comparator v bg > cxina compare cx v in - v in + coe v bg /6 c x ina cxout pin comparator cxind > cxina compare cx v in - v in + coe cxout v ref + c x ina pin cvrefm<1:0> = xx cvrefm<1:0> = xx cvrefm<1:0> = 01 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 11 cen = 1 , cch<1:0> = 01 cvrefm<1:0> = xx cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 00 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 10
? 2010 microchip technology inc. ds39975a-page 313 pic24fj256gb210 family figure 23-3: individual comparator configurations when cref = 1 and cvrefp = 0 figure 23-4: individual comparator configurations when cref = 1 and cvrefp = 1 comparator cxind > cv ref compare cx v in - v in + coe c x ind cv ref cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg cv ref cxout pin comparator cxinc > cv ref compare cx v in - v in + coe c x inc cv ref cxout pin comparator cxinb > cv ref compare cen = 1 , cch<1:0> = 00 cx v in - v in + coe c x inb cv ref cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg /2 cv ref cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg /6 cv ref cxout pin comparator cxind > cv ref compare cx v in - v in + coe v ref + cv ref cxout pin cvrefm<1:0> = xx cen = 1 , cch<1:0> = 10 cvrefm<1:0> = xx cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 01 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 11 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 10 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 00 cen = 1 , cch<1:0> = 01 cvrefm<1:0> = xx comparator cxind > cv ref compare cx v in - v in + coe c x ind v ref + cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg v ref + cxout pin comparator cxinc > cv ref compare cx v in - v in + coe c x inc v ref + cxout pin comparator cxinb > cv ref compare cx v in - v in + coe c x inb v ref + cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg /2 v ref + cxout pin comparator v bg > cv ref compare cx v in - v in + coe v bg /6 v ref + cxout pin cen = 1 , cch<1:0> = 00 cvrefm<1:0> = xx cen = 1 , cch<1:> = 10 cvrefm<1:0> = xx cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 01 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 10 cen = 1 , cch<1:0> = 11 cvrefm<1:0> = 00 cen = 1 , cch<1:0> = 01 cvrefm<1:0> = xx
pic24fj256gb210 family ds39975a-page 314 ? 2010 microchip technology inc. register 23-1: cmxcon: comp arator x control registers (comparators 1 through 3) r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0, hs r-0, hsc cen coe cpol ? ? ? cevt cout bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 evpol1 evpol0 ? cref ? ? cch1 cch0 bit 7 bit 0 legend: hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cen: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled bit 14 coe: comparator output enable bit 1 = comparator output is present on the cxout pin 0 = comparator output is internal only bit 13 cpol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 12-10 unimplemented: read as ? 0 ? bit 9 cevt: comparator event bit 1 = comparator event that is defined by evpol<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = comparator event has not occurred bit 8 cout: comparator output bit when cpol = 0 : 1 =v in + > v in - 0 =v in + < v in - when cpol = 1 : 1 =v in + < v in - 0 =v in + > v in - bit 7-6 evpol<1:0>: trigger/event/interrupt polarity select bits 11 = trigger/event/interrupt is generated on any change of the comparator output (while cevt = 0 ) 10 = trigger/event/interrupt is generated on transition of the comparator output: if cpol = 0 (non-inverted polarity): high-to-low transition only. if cpol = 1 (inverted polarity): low-to-high transition only. 01 = trigger/event/interrupt is generated on transition of comparator output: if cpol = 0 (non-inverted polarity): low-to-high transition only. if cpol = 1 (inverted polarity): high-to-low transition only. 00 = trigger/event/interrupt generation is disabled bit 5 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 315 pic24fj256gb210 family bit 4 cref: comparator reference select bits (non-inverting input) 1 = non-inverting input connects to the internal cv ref voltage 0 = non-inverting input connects to the c x ina pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator channel select bits 11 = inverting input of the comparator connects to the internal selectable reference voltage specified by the cvrefm<1:0> bits in the cvrcon register 10 = inverting input of the comparator connects to the c x ind pin 01 = inverting input of the comparator connects to the c x inc pin 00 = inverting input of the comparator connects to the c x inb pin register 23-1: cmxcon: comp arator x control registers (comparators 1 through 3) (continued) register 23-2: cmstat: comparat or module status register r/w-0 u-0 u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc cmidl ? ? ? ? c3evt c2evt c1evt bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc ? ? ? ? ? c3out c2out c1out bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cmidl: comparator stop in idle mode bit 1 = discontinue operation of all comparators when device enters idle mode 0 = continue operation of all enabled comparators in idle mode bit 14-11 unimplemented: read as ? 0 ? bit 10 c3evt: comparator 3 event status bit (read-only) shows the current event status of comparator 3 (cm3con<9>). bit 9 c2evt: comparator 2 event status bit (read-only) shows the current event status of comparator 2 (cm2con<9>). bit 8 c1evt: comparator 1 event status bit (read-only) shows the current event status of comparator 1 (cm1con<9>). bit 7-3 unimplemented: read as ? 0 ? bit 2 c3out: comparator 3 output status bit (read-only) shows the current output of comparator 3 (cm3con<8>). bit 1 c2out: comparator 2 output status bit (read-only) shows the current output of comparator 2 (cm2con<8>). bit 0 c1out: comparator 1 output status bit (read-only) shows the current output of comparator 1 (cm1con<8>).
pic24fj256gb210 family ds39975a-page 316 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 317 pic24fj256gb210 family 24.0 comparator voltage reference 24.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register (register 24-1). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr<3:0>), with one range offering finer resolution. the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref -. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output. figure 24-1: comparator voltage reference block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ? pic24f family reference manual ?, section 19. ?comparator module? (ds39710). the information in this data sheet supersedes the information in the frm. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref av ss cvroe c vref pin
pic24fj256gb210 family ds39975a-page 318 ? 2010 microchip technology inc. register 24-1: cvrcon: comparator vo ltage reference control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? cvrefp cvrefm1 cvrefm0 bit 15 bit 8 r/w -0 r/w -0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 cvrefp: voltage reference select bit (valid only when cref is ? 1 ?) 1 =v ref + is used as a reference voltage to the comparators 0 = the cvr (4-bit dac) within this module provides the the reference voltage to the comparators bit 9-8 cvrefm<1:0>: band gap reference source select bits (valid only when cch<1:0> = 11 ) 00 = band gap voltage is provided as an input to the comparators 01 = band gap voltage divided-by-two is provided as an input to the comparators 10 = band gap voltage divided-by-six is provided as an input to the comparators 11 =v ref + pin is provided as an input the comparators bit 7 cvren: comparator voltage reference enable bit 1 =cv ref circuit is powered on 0 =cv ref circuit is powered down bit 6 cvroe: comparator v ref output enable bit 1 = cvref voltage level is output on the cv ref pin 0 = cvref voltage level is disconnected from the cv ref pin bit 5 cvrr: comparator v ref range selection bit 1 =cv rsrc range should be 0 to 0.625 cv rsrc with cv rsrc /24 step size 0 =cv rsrc range should be 0.25 to 0.719 cv rsrc with cv rsrc /32 step size bit 4 cvrss: comparator v ref source selection bit 1 = comparator reference source, cv rsrc = v ref + ? v ref - 0 = comparator reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0>: comparator v ref value selection 0 ? cvr<3:0> ? 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/ 24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc )
? 2010 microchip technology inc. ds39975a-page 319 pic24fj256gb210 family 25.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. its key features include: ? four edge input trigger sources ? polarity control for each edge source ? control of edge sequence ? control of response to edges ? time measurement resolution of 1 nanosecond ? accurate current source suitable for capacitive measurement together with other on-chip analog modules, the ctmu can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. the ctmu module is ideal for interfacing with capacitive-based sensors. the ctmu is controlled through two registers: ctmucon and ctmuicon. ctmucon enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. the ctmuicon register controls the selection and trim of the current source. 25.1 measuring capacitance the ctmu module measures capacitance by generat- ing an output pulse with a width equal to the time between edge events on two separate input channels. the pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (oc1 and timer1) and two external pins (ctedg1 and ctedg2). this pulse is used with the module?s precision current source to calculate capacitance according to the relationship: for capacitance measurements, the a/d converter samples an external capacitor (c app ) on one of its input channels after the ctmu output?s pulse. a preci- sion resistor (r pr ) provides current source calibration on a second a/d channel. after the pulse ends, the converter determines the voltage on the capacitor. the actual calculation of capacitance is performed in software by the application. figure 25-1 shows the external connections used for capacitance measurements, and how the ctmu and a/d modules are related in this application. this example also shows the edge events coming from timer1, but other configurations using external edge sources are possible. a detailed discussion on measur- ing capacitance and time with the ctmu module is provided in the ? pic24f family reference manual ?. figure 25-1: typical connections and internal configuration for capacitance measurement note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the associated ? pic24f family reference manual ?, section 11. ?charge time measurement unit (ctmu)? (ds39724). the information in this data sheet supersedes the information in the frm. ci dv dt ------ - ? = pic24f device a/d converter ctmu anx c app output pulse edg1 edg2 r pr an y timer1 current source
pic24fj256gb210 family ds39975a-page 320 ? 2010 microchip technology inc. 25.2 measuring time time measurements on the pulse width can be similarly performed using the a/d module?s internal capacitor (c ad ) and a precision resistor for current calibration. figure 25-2 shows the external connections used for time measurements, and how the ctmu and a/d modules are related in this application. this example also shows both edge events coming from the external ctedg pins, but other configurations using internal edge sources are possible. a detailed discussion on measuring capacitance and time with the ctmu module is provided in the ? pic24f family reference manual ?. 25.3 pulse generation and delay the ctmu module can also generate an output pulse with edges that are not synchronous with the device?s system clock. more specifically, it can generate a pulse with a programmable delay from an edge event input to the module. when the module is configured for pulse generation delay by setting the tgen (ctmucon<12>) bit, the internal current source is connected to the b input of comparator 2. a capacitor (c delay ) is connected to the comparator 2 pin, c2inb, and the comparator volt- age reference, cv ref , is connected to c2ina. cv ref is then configured for a specific trip point. the module begins to charge c delay when an edge event is detected. when c delay charges above the cv ref trip point, a pulse is output on ctpls. the length of the pulse delay is determined by the value of c delay and the cv ref trip point. figure 25-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. while ctedg1 is shown as the input pulse source, other options are available. a detailed discussion on pulse generation with the ctmu module is provided in the ? pic24f family reference manual? . figure 25-2: typical connections and internal configuration for time measurement figure 25-3: typical co nnections and internal co nfiguration for pulse delay generation pic24f device a/d converter ctmu ctedg1 ctedg2 anx output pulse edg1 edg2 c ad r pr current source c2 cv ref ctpls pic24f device current source comparator ctmu ctedg1 c2inb c delay edg1
? 2010 microchip technology inc. ds39975a-page 321 pic24fj256gb210 family register 25-1: ctmucon: ctmu control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmuen ?ctmusidltgen (1) edgen edgseqen idissen cttrig bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0, hsc r/w-0, hsc edg2pol edg2sel1 edg2sel0 edg1pol ed g1sel1 edg1sel0 edg2stat edg1stat bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ctmuen: ctmu enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ctmusidl: stop in idle mode bit 1 = discontinue module operation when the device enters idle mode 0 = continue module operation in idle mode bit 12 tgen: time generation enable bit (1) 1 = enables edge delay generation 0 = disables edge delay generation bit 10 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked bit 10 edgseqen: edge sequence enable bit 1 = edge 1 event must occur before edge 2 event can occur 0 = no edge sequence is needed bit 9 idissen: analog current source control bit 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 8 cttrig: trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled bit 7 edg2pol: edge 2 polarity select bit 1 = edge 2 is programmed for a positive edge response 0 = edge 2 is programmed for a negative edge response bit 6-5 edg2sel<1:0>: edge 2 source select bits 11 =ctedg1 pin 10 =ctedg2 pin 01 = oc1 module 00 = timer1 module bit 4 edg1pol: edge 1 polarity select bit 1 = edge 1 is programmed for a positive edge response 0 = edge 1 is programmed for a negative edge response note 1: if tgen = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information.
pic24fj256gb210 family ds39975a-page 322 ? 2010 microchip technology inc. bit 3-2 edg1sel<1:0>: edge 1 source select bits 11 =ctedg1 pin 10 =ctedg2 pin 01 = oc1 module 00 = timer1 module bit 1 edg2stat: edge 2 status bit 1 = edge 2 event has occurred 0 = edge 2 event has not occurred bit 0 edg1stat: edge 1 status bit 1 = edge 1 event has occurred 0 = edge 1 event has not occurred register 25-1: ctmuco n: ctmu control register (continued) note 1: if tgen = 1 , the peripheral inputs and outputs must be configured to an available rpn/rpin pin. see section 10.4 ?peripheral pin select (pps)? for more information. register 25-2: ctmuicon: ctmu current control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 . . . 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current . . . 100010 100001 = maximum negative change from nominal current bit 9-8 irng<1:0>: current source range select bits 11 = 100 ? base current 10 =10 ? base current 01 = base current level (0.55 ? a nominal) 00 = current source is disabled bit 7-0 unimplemented: read as ? 0 ?
? 2010 microchip technology inc. ds39975a-page 323 pic24fj256gb210 family 26.0 special features pic24fj256gb210 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection ? jtag boundary scan interface ? in-circuit serial programming? ? in-circuit emulation 26.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location f80000h. a detailed explana- tion of the various bit functions is provided in register 26-1 through register 26-6. note that address f80000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (800000h-ffffffh) which can only be accessed using table reads and table writes. 26.1.1 considerations for configuring pi c24fj256gb210 family devices in pic24fj256gb210 family devices, the configuration bytes are implemented as volatile memory. this means that configuration data must be programmed each time the device is powered up. configuration data is stored in the three words at the top of the on-chip program memory space, known as the flash configuration words. their specific locations are shown in table 26-1. these are packed representations of the actual device configuration bits, whose actual locations are distributed among several locations in configuration space. the configuration data is automat- ically loaded from the flash configuration words to the proper configuration registers during device resets. when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the upper byte of all flash configuration words in pro- gram memory should always be ? 0000 0000 ?. this makes them appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 0 ?s to these locations has no effect on device operation. table 26-1: flash configuration word locations for pic24fj256gb210 family devices note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the following sections of the ? pic24f family reference manual ?. the information in this data sheet supersedes the information in the frms. ? section 9. ?watchdog timer (wdt)? (ds39697) ? section 32. ?high-level device integration? (ds39719) ? section 33. ?programming and diagnostics? (ds39716) note: configuration data is reloaded on all types of device resets. note: performing a page erase operation on the last page of program memory clears the flash configuration words, enabling code protection as a result. therefore, users should avoid performing page erase operations on the last page of program memory. device configuration word addresses 1234 pic24fj128gb2xx 157feh 157fch 157fah 157f8h pic24fj256gb2xx 2abfeh 2abfch 2abfah 2abf8h
pic24fj256gb210 family ds39975a-page 324 ? 2010 microchip technology inc. register 26-1: cw1: flash configuration word 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 r-x r/po-1 r/po-1 r/po-1 r/po-1 r-1 r/po-1 r/po-1 reserved jtagen gcp gwrp debug reserved ics1 ics0 bit 15 bit 8 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 fwdten windis altvref (1) fwpsa wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 1 ? bit 15 reserved: the value is unknown; program as ? 0 ? bit 14 jtagen: jtag port enable bit 1 = jtag port is enabled 0 = jtag port is disabled bit 13 gcp: general segment program memory code protection bit 1 = code protection is disabled 0 = code protection is enabled for the entire program memory space bit 12 gwrp: general segment code flash write protection bit 1 = writes to program memory are allowed 0 = writes to program memory are not allowed bit 11 debug : background debugger enable bit 1 = device resets into operational mode 0 = device resets into debug mode bit 10 reserved: always maintain as ? 1 ? bit 9-8 ics<1:0>: emulator pin placement select bits 11 = emulator functions are shared with pgec1/pged1 10 = emulator functions are shared with pgec2/pged2 01 = emulator functions are shared with pgec3/pged3 00 = reserved; do not use bit 7 fwdten: watchdog timer enable bit 1 = watchdog timer is enabled 0 = watchdog timer is disabled bit 6 windis: windowed watchdog timer disable bit 1 = standard watchdog timer is enabled 0 = windowed watchdog timer is enabled; fwdten must be ? 1 ? bit 5 altvref : alternate v ref pin selection bit (1) 1 =v ref is on a default pin (v ref + on ra10 and v ref - on ra9) 0 =v ref is on an alternate pin (v ref + on rb0 and v ref - on rb1) note 1: unimplemented in 64-pin devices, maintain at ? 1 ? (v ref + on rb0 and v ref - on rb1).
? 2010 microchip technology inc. ds39975a-page 325 pic24fj256gb210 family bit 4 fwpsa: wdt prescaler ratio select bit 1 = prescaler ratio of 1:128 0 = prescaler ratio of 1:32 bit 3-0 wdtps<3:0>: watchdog timer postscaler select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 register 26-1: cw1: flash configuration word 1 (continued) note 1: unimplemented in 64-pin devices, maintain at ? 1 ? (v ref + on rb0 and v ref - on rb1).
pic24fj256gb210 family ds39975a-page 326 ? 2010 microchip technology inc. register 26-2: cw2: flash configuration word 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 ieso plldiv2 plldiv1 plldiv0 pll96mhz fnosc2 fnosc1 fnosc0 bit 15 bit 8 r/po-1 r/po-1 r/po-1 r/po-1 r-1 r-1 r/po-1 r/po-1 fcksm1 fcksm0 osciofcn iol1way reserved reserved poscmd1 poscmd0 bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 1 ? bit 15 ieso: internal external switchover bit 1 = ieso mode (two-speed start-up) is enabled 0 = ieso mode (two-speed start-up) is disabled bit 14-12 plldiv<2:0>: 96 mhz pll prescaler select bits 111 = oscillator input is divided by 12 (48 mhz input) 110 = oscillator input is divided by 8 (32 mhz input) 101 = oscillator input is divided by 6 (24 mhz input) 100 = oscillator input is divided by 5 (20 mhz input) 011 = oscillator input is divided by 4 (16 mhz input) 010 = oscillator input is divided by 3 (12 mhz input) 001 = oscillator input is divided by 2 (8 mhz input) 000 = oscillator input is used directly (4 mhz input) bit 11 pll96mhz: 96 mhz pll start-up enable bit 1 = 96 mhz pll is enabled automatically on start-up 0 = 96 mhz pll is software controlled (can be enabled by setting the pllen bit (clkdiv<5>)) bit 10-8 fnosc<2:0>: initial oscillator select bits 111 = fast rc oscillator with postscaler (frcdiv) 110 = reserved 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator with postscaler and pll module (frcpll) 000 = fast rc oscillator (frc) bit 7-6 fcksm<1:0>: clock switching and fail-safe clock monitor configuration bits 1x = clock switching and fail-safe clock monitor are disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 5 osciofcn: osco pin configuration bit if poscmd < 1: 0> = 11 or 00 : 1 = osco/clko/rc15 functions as clko (f osc /2) 0 = osco/clko/rc15 functions as port i/o (rc15) if poscmd < 1: 0> = 10 or 01 : osciofcn has no effect on osco/clko/rc15.
? 2010 microchip technology inc. ds39975a-page 327 pic24fj256gb210 family bit 4 iol1way: iolock one-way set enable bit 1 = the iolock bit (osccon<6>) can be set once, provided the unlock sequence has been completed. once set, the peripheral pin select registers cannot be written to a second time. 0 = the iolock bit can be set and cleared as needed, provided the unlock sequence has been completed bit 3-2 reserved: always maintain as ? 1 ? bit 1-0 poscmd<1:0>: primary oscillator configuration bits 11 = primary oscillator is disabled 10 = hs oscillator mode is selected 01 = xt oscillator mode is selected 00 = ec oscillator mode is selected register 26-2: cw2: flash configuration word 2 (continued) register 26-3: cw3: flash configuration word 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 wpend wpcfg wpdis altpmp (1) wutsel1 wutsel0 soscsel1 soscsel0 bit 15 bit 8 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 r/po-1 wpfp7 wpfp6 wpfp5 wpfp4 wpfp3 wpfp2 wpfp1 wpfp0 bit 7 bit 0 legend: po = program-once bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 1 ? bit 15 wpend: segment write protection end page select bit 1 = protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by wpfp<7:0> 0 = protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by wpfp<7:0> bit 14 wpcfg: configuration word code page write protection select bit 1 = last page (at the top of program memory) and flash configuration words are not write-protected (3) 0 = last page and flash configuration words are write-protected, provided wpdis = ? 0 ? bit 13 wpdis: segment write protection disable bit 1 = segmented code protection is disabled 0 = segmented code protection is enabled; protected segment is defined by the wpend, wpcfg and wpfpx configuration bits bit 12 altpmp: alternate epmp pin mapping bit (1) 1 = epmp pins are in default location mode 0 = epmp pins are in alternate location mode note 1: unused in 64-pin devices, maintain at ? 1 ?. 2: ensure that the sclki pin is made a digital input while using this configuration, see table 10-2. 3: regardless of wpcfg status, if wpend = 1 or if wpfp corresponds to the configuration word?s page, the configuration word?s page is protected.
pic24fj256gb210 family ds39975a-page 328 ? 2010 microchip technology inc. bit 11-10 wutsel<1:0>: voltage regulator standby mode wake-up time select bits 11 = default regulator start-up time is used 01 = fast regulator start-up time is used x0 = reserved; do not use bit 9-8 soscsel<1:0>: sosc selection configuration bits 11 = secondary oscillator is in default (high drive strength) oscillator mode 10 = reserved; do not use 01 = secondary oscillator is in low-power (low drive strength) oscillator mode 00 = external clock (sclki) or digital i/o mode (2) bit 7-0 wpfp<7:0>: write protected code segment boundary page bits designates the 512 instruction words page boundary of the protected code segment. if wpend = 1 : specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. if wpend = 0 : specifies the upper page boundary of the code-protected segment; page 0 being the lower boundary. register 26-3: cw3: flash configuration word 3 (continued) note 1: unused in 64-pin devices, maintain at ? 1 ?. 2: ensure that the sclki pin is made a digital input while using this configuration, see table 10-2. 3: regardless of wpcfg status, if wpend = 1 or if wpfp corresponds to the configuration word?s page, the configuration word?s page is protected. register 26-4: cw4: flash configuration word 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 15 bit 8 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 reserved reserved reserved reserved reserved reserved reserved reserved bit 7 bit 0 legend: r = reserved bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 0 ? bit 15-0 reserved: always maintain as ? 1 ?
? 2010 microchip technology inc. ds39975a-page 329 pic24fj256gb210 family register 26-5: devid: device id register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 rrrrrrrr famid7 famid6 famid5 famid4 famid3 famid2 famid1 famid0 bit 15 bit 8 rrrrrrrr dev7 dev6 dev5 dev4 dev3 dev2 dev1 dev0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit bit 23-16 unimplemented: read as ? 1 ? bit 15-8 famid<7:0>: device family identifier bits 01000001 = pic24fj256gb210 family bit 7-0 dev<7:0>: individual device identifier bits 00000000 = pic24fj128gb206 00000010 = PIC24FJ128GB210 00000100 = pic24fj256gb206 00000110 = pic24fj256gb210 register 26-6: devrev: device revision register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r r r r ? ? ? ? rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = readable bit u = unimplemented bit bit 23-4 unimplemented: read as ? 0 ? bit 3-0 rev<3:0>: device revision identifier bits
pic24fj256gb210 family ds39975a-page 330 ? 2010 microchip technology inc. 26.2 on-chip voltage regulator all pic24fj256gb210 family devices power their core digital logic at a nominal 1.8v. this may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the pic24fj256gb210 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is controlled by the envreg pin. tying v dd to the pin enables the regulator, which in turn, provides power to the core from the other v dd pins. when the reg- ulator is enabled, a low-esr capacitor (such as ceramic) must be connected to the v cap pin (figure 26-1). this helps to maintain the stability of the regulator. the recom- mended value for the filter capacitor (c efc ) is provided in section 29.1 ?dc characteristics? . 26.2.1 voltage regulator low-voltage detection when the on-chip regulator is enabled, it provides a constant voltage of 1.8v nominal to the digital core logic. the regulator can provide this level from a v dd of about 2.1v, all the way up to the device?s v ddmax . it does not have the capability to boost v dd levels. in order to pre- vent ?brown-out? conditions when the voltage drops too low for the regulator, the brown-out reset occurs. then the regulator output follows v dd with a typical voltage drop of 300 mv. to provide information about when the regulator voltage starts reducing, the on-chip regulator includes a simple low-voltage detect circuit, which sets the low-voltage detect interrupt flag, lvdif (ifs4<8>). this can be used to generate an interrupt to trigger an orderly shutdown. figure 26-1: conne ctions for the on-chip regulator 26.2.2 on-chip regulator and por when the voltage regulator is enabled, it takes approx- imately 10 ? s for it to generate output. during this time, designated as t vreg , code execution is disabled. t vreg is applied every time the device resumes operation after any power-down, including sleep mode. t vreg is determined by the status of the vregs bit (rcon<8>) and the wutsel configuration bits (cw3<11:10>). refer to section 29.0 ?electrical characteristics? for more information on t vreg . 26.2.3 on-chip regulator and bor when the on-chip regulator is enabled, pic24fj256gb210 family devices also have a simple brown-out capability. if the voltage supplied to the reg- ulator is inadequate to maintain the output level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor (rcon<1>) flag bit. the brown-out voltage specifications are provided in section 7. ?reset? (ds39712) in the ? pic24f family reference manual ?. 26.2.4 voltage regulator standby mode when enabled, the on-chip regulator always consumes a small incremental amount of current over i dd /i pd , including when the device is in sleep mode, even though the core digital logic does not require power. to provide additional savings in applications where power resources are critical, the regulator can be made to enter standby mode on its own whenever the device goes into sleep mode. this feature is controlled by the vregs bit (rcon<8>). clearing the vregs bit enables the standby mode. when waking up from standby mode, the regulator needs to wait for t vreg to expire before wake-up. the regulator wake-up time required for standby mode is controlled by the wutsel<1:0> (cw3<11:10>) configuration bits. the regulator wake-up time is lower when wutsel<1:0> = 01 , and higher when wutsel<1:0> = 11 . refer to the t vreg specification in table 29-10 for regulator wake-up time. when the regulator?s standby mode is turned off (vregs = 1 ), the device wakes up without waiting for tv reg . however, with the vregs bit set, the power consumption while in sleep mode will be approximately 40 ? a higher than what it would be if the regulator was allowed to enter standby mode. v dd envreg v cap v ss pic24fjxxxgb2xx c efc 3.3v (1) regulator enabled (envreg tied to v dd ): note 1: this is a typical operating voltage. refer to section 29.1 ?dc characteristics? for the full operating ranges of v dd . (10 ? f typ) note: for more information, see section 29.0 ?electrical characteristics? . the infor- mation in this data sheet supersedes the information in the frm.
? 2010 microchip technology inc. ds39975a-page 331 pic24fj256gb210 family 26.3 watchdog timer (wdt) for pic24fj256gb210 family devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt clock source from lprc is 31 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the fwpsa configuration bit. with a 31 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtps<3:0> con- figuration bits (cw1<3:0>), which allows the selection of a total of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will continue from where the pwrsav instruction was executed. the corresponding sleep or idle (rcon<3:2>) bit will need to be cleared in software after the device wakes up. the wdt flag bit, wdto (rcon<4>), is not auto- matically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. 26.3.1 windowed operation the watchdog timer has an optional fixed-window mode of operation. in this windowed mode, clrwdt instructions can only reset the wdt during the last 1/4 of the programmed wdt period. a clrwdt instruction executed before that window causes a wdt reset, similar to a wdt time-out. windowed wdt mode is enabled by programming the windis configuration bit (cw1<6>) to ? 0 ?. 26.3.2 control register the wdt is enabled or disabled by the fwdten configuration bit. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. figure 26-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. lprc input wdt overflow wake from sleep 31 khz prescaler postscaler fwpsa swdten fwdten reset all device resets sleep or idle mode lprc control clrwdt instr. pwrsav instr. (5-bit/7-bit) 1:1 to 1:32.768 wdtps<3:0> 1 ms/4 ms exit sleep or idle mode wdt counter transition to new clock source
pic24fj256gb210 family ds39975a-page 332 ? 2010 microchip technology inc. 26.4 program verification and code protection pic24fj256gb210 family devices provide two compli- mentary methods to protect application code from overwrites and erasures. these also help to protect the device from inadvertent configuration changes during run time. 26.4.1 general segment protection for all devices in the pic24fj256gb210 family, the on-chip program memory space is treated as a single block, known as the general segment (gs). code pro- tection for this block is controlled by one configuration bit, gcp. this bit inhibits external reads and writes to the program memory space. it has no direct effect in normal execution mode. write protection is controlled by the gwrp bit in the configuration word. when gwrp is programmed to ? 0 ?, internal write and erase operations to program memory are blocked. 26.4.2 code segment protection in addition to global general segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. this area can be used for many purposes where a sep- arate block of write and erase-protected code is needed, such as bootloader applications. unlike common boot block implementations, the specially protected segment in the pic24fj256gb210 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. code segment protection provides an added level of protection to a designated area of program memory by disabling the nvm safety interlock whenever a write or erase address falls within a specified range. it does not override general segment protection controlled by the gcp or gwrp bits. for example, if gcp and gwrp are enabled, enabling segmented code protection for the bottom half of program memory does not undo the general segment protection for the top half. the size and type of protection for the segmented code range are configured by the wpfpx, wpend, wpcfg and wpdis bits in configuration word 3. code seg- ment protection is enabled by programming the wpdis bit (= 0 ). the wpfp bits specify the size of the segment to be protected by specifying the 512-word code page that is the start or end of the protected segment. the specified region is inclusive, therefore, this page will also be protected. the wpend bit determines if the protected segment uses the top or bottom of the program space as a boundary. programming wpend (= 0 ) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. leaving wpend unpro- grammed (= 1 ) protects the specified page through the last page of implemented program memory, including the configuration word locations. a separate bit, wpcfg, is used to protect the last page of program space, including the flash configuration words. programming wpcfg (= 0 ) protects the last page in addition to the pages selected by the wpend and wpfp<7:0> bits setting. this is useful in circum- stances where write protection is needed for both the code segment in the bottom of the memory and the flash configuration words. the various options for segment code protection are shown in table 26-2.
? 2010 microchip technology inc. ds39975a-page 333 pic24fj256gb210 family 26.4.3 configuration register protection the configuration registers are protected against inadvertent or unwanted changes or reads in two ways. the primary protection method is the same as that of the rp registers ? shadow registers contain a compli- mentary value which is constantly compared with the actual value. to safeguard against unpredictable events, configura- tion bit changes resulting from individual cell level disruptions (such as esd events) will cause a parity error and trigger a device reset. the data for the configuration registers is derived from the flash configuration words in program memory. when the gcp bit is set, the source data for device configuration is also protected as a consequence. even if general segment protection is not enabled, the device configuration can be protected by using the appropriate code segment protection setting. table 26-2: code segment prot ection configuration options 26.5 jtag interface pic24fj256gb210 family devices implement a jtag interface, which supports boundary scan device testing. 26.6 in-circuit serial programming? pic24fj256gb210 family microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock (pgecx) and data (pgedx), and three other lines for power (v dd ), ground (v ss ) and mclr . this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 26.7 in-circuit debugger when mplab ? icd 3 is selected as a debugger, the in-circuit debugging functionality is enabled. this func- tion allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the pgecx (emulation/debug clock) and pgedx (emulation/debug data) pins. to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss and the pgecx/pgedx pin pair des- ignated by the ics configuration bits. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. segment configuration bits write/erase protection of code segment wpdis wpend wpcfg 1xx no additional protection is enabled; all program memory protection is configured by gcp and gwrp. 01x addresses from the first address of the code page are defined by wpfp<7:0> through the end of implemented program memory (inclusive), write/erase protected, including flash configuration words. 001 address 000000h through the last address of the code page is defined by wpfp<7:0> (inclusive), write/erase protected. 000 address 000000h through the last address of code page is defined by wpfp<7:0> (inclusive), write/erase protected and the last page, including flash configuration words are write/erase protected.
pic24fj256gb210 family ds39975a-page 334 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 335 pic24fj256gb210 family 27.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 27.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic24fj256gb210 family ds39975a-page 336 ? 2010 microchip technology inc. 27.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 27.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 27.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 27.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2010 microchip technology inc. ds39975a-page 337 pic24fj256gb210 family 27.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 27.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj11) or with the new high-speed, noise tolerant, low-voltage differential sig- nal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. 27.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip?s most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy-to-use graphical user interface of mplab inte- grated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 27.10 pickit 3 in-circuit debugger/programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer?s pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic24fj256gb210 family ds39975a-page 338 ? 2010 microchip technology inc. 27.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 27.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 27.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2010 microchip technology inc. ds39975a-page 339 pic24fj256gb210 family 28.0 instruction set summary the pic24f instruction set adds many enhancements to the previous pic ? mcu instruction sets, while main- taining an easy migration from previous pic mcu instruction sets. most instructions are a single program memory word. only three instructions require two program memory locations. each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? control operations table 28-1 shows the general symbols used in describing the instructions. the pic24f instruction set summary in table 28-2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: ? the first source operand which is typically a register ?wb? without any address modifier ? the second source operand which is typically a register ?ws? with or without an address modifier ? the destination of the result which is typically a register ?wd? with or without an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value, ?f? ? the destination, which could either be the file register, ?f?, or the w0 register, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register, ?wb?) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand which is a register ?wb? without any address modifier ? the second source operand which is a literal value ? the destination of the result (only if not the same as the first source operand), which is typically a register ?wd? with or without an address modifier the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions all instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required infor- mation is available in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes, and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: this chapter is a brief summary of the pic24f instruction set architecture and is not intended to be a comprehensive reference source.
pic24fj256gb210 family ds39975a-page 340 ? 2010 microchip technology inc. table 28-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) ?? {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address ?? {0000h...1fffh} lit1 1-bit unsigned literal ?? {0,1} lit4 4-bit unsigned literal ?? {0...15} lit5 5-bit unsigned literal ?? {0...31} lit8 8-bit unsigned literal ?? {0...255} lit10 10-bit unsigned literal ?? {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal ?? {0...16383} lit16 16-bit unsigned literal ?? {0...65535} lit23 23-bit unsigned literal ?? {0...8388607}; lsb must be ? 0 ? none field does not require an entry, may be blank pc program counter slit10 10-bit signed literal ?? {-512...511} slit16 16-bit signed literal ?? {-32768...32767} slit6 6-bit signed literal ?? {-16...16} wb base w register ?? {w0..w15} wd destination w register ?? { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register ?? { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working r egister pair (direct addressing) wn one of 16 working registers ?? {w0..w15} wnd one of 16 destination working registers ?? {w0..w15} wns one of 16 source working registers ?? {w0..w15} wreg w0 (working register used in file register instructions) ws source w register ?? { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register ?? { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] }
? 2010 microchip technology inc. ds39975a-page 341 pic24fj256gb210 family table 28-2: instruction set overview assembly mnemonic assembly syntax description # of words # of cycles status flags affected add add f f = f + wreg 1 1 c, dc, n, ov, z add f,wreg wreg = f + wreg 1 1 c, dc, n, ov, z add #lit10,wn wd = lit10 + wd 1 1 c, dc, n, ov, z add wb,ws,wd wd = wb + ws 1 1 c, dc, n, ov, z add wb,#lit5,wd wd = wb + lit5 1 1 c, dc, n, ov, z addc addc f f = f + wreg + (c) 1 1 c, dc, n, ov, z addc f,wreg wreg = f + wreg + (c) 1 1 c, dc, n, ov, z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c, dc, n, ov, z addc wb,ws,wd wd = wb + ws + (c) 1 1 c, dc, n, ov, z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c, dc, n, ov, z and and f f = f .and. wreg 1 1 n, z and f,wreg wreg = f .and. wreg 1 1 n, z and #lit10,wn wd = lit10 .and. wd 1 1 n, z and wb,ws,wd wd = wb .and. ws 1 1 n, z and wb,#lit5,wd wd = wb .and. lit5 1 1 n, z asr asr f f = arithmetic right shift f 1 1 c, n, ov, z asr f,wreg wreg = arithmetic right shift f 1 1 c, n, ov, z asr ws,wd wd = arithmetic right shift ws 1 1 c, n, ov, z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n, z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n, z bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none
pic24fj256gb210 family ds39975a-page 342 ? 2010 microchip technology inc. btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clrwdt clrwdt clear watchdog timer 1 1 wdto, sleep com com f f = f 11n, z com f,wreg wreg = f 11n, z com ws,wd wd = ws 11n, z cp cp f compare f with wreg 1 1 c, dc, n, ov, z cp wb,#lit5 compare wb with lit5 1 1 c, dc, n, ov, z cp wb,ws compare wb with ws (wb ? ws) 1 1 c, dc, n, ov, z cp0 cp0 f compare f with 0x0000 1 1 c, dc, n, ov, z cp0 ws compare ws with 0x0000 1 1 c, dc, n, ov, z cpb cpb f compare f with wreg, with borrow 1 1 c, dc, n, ov, z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c, dc, n, ov, z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c, dc, n, ov, z cpseq cpseq wb,wn compare wb with wn, skip if = 1 1 (2 or 3) none cpsgt cpsgt wb,wn compare wb with wn, skip if > 1 1 (2 or 3) none cpslt cpslt wb,wn compare wb with wn, skip if < 1 1 (2 or 3) none cpsne cpsne wb,wn compare wb with wn, skip if ? 11 (2 or 3) none daw daw.b wn wn = decimal adjust wn 1 1 c dec dec f f = f ?1 1 1 c, dc, n, ov, z dec f,wreg wreg = f ?1 1 1 c, dc, n, ov, z dec ws,wd wd = ws ? 1 1 1 c, dc, n, ov, z dec2 dec2 f f = f ? 2 1 1 c, dc, n, ov, z dec2 f,wreg wreg = f ? 2 1 1 c, dc, n, ov, z dec2 ws,wd wd = ws ? 2 1 1 c, dc, n, ov, z disi disi #lit14 disable interrupts for k instruction cycles 1 1 none div div.sw wm,wn signed 16/16-bit integer divide 1 18 n, z, c, ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n, z, c, ov div.uw wm,wn unsigned 16/16-bit integer divide 1 18 n, z, c, ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n, z, c, ov exch exch wns,wnd swap wns with wnd 1 1 none ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2010 microchip technology inc. ds39975a-page 343 pic24fj256gb210 family goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none inc inc f f = f + 1 1 1 c, dc, n, ov, z inc f,wreg wreg = f + 1 1 1 c, dc, n, ov, z inc ws,wd wd = ws + 1 1 1 c, dc, n, ov, z inc2 inc2 f f = f + 2 1 1 c, dc, n, ov, z inc2 f,wreg wreg = f + 2 1 1 c, dc, n, ov, z inc2 ws,wd wd = ws + 2 1 1 c, dc, n, ov, z ior ior f f = f .ior. wreg 1 1 n, z ior f,wreg wreg = f .ior. wreg 1 1 n, z ior #lit10,wn wd = lit10 .ior. wd 1 1 n, z ior wb,ws,wd wd = wb .ior. ws 1 1 n, z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n, z lnk lnk #lit14 link frame pointer 1 1 none lsr lsr f f = logical right shift f 1 1 c, n, ov, z lsr f,wreg wreg = logical right shift f 1 1 c, n, ov, z lsr ws,wd wd = logical right shift ws 1 1 c, n, ov, z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n, z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n, z mov mov f,wn move f to wn 1 1 none mov [wns+slit10],wnd move [wns+slit10] to wnd 1 1 none mov f move f to f 1 1 n, z mov f,wreg move f to wreg 1 1 n, z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wns,[wns+slit10] move wns to [wns+slit10] 1 1 mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n, z mov.d wns,wd move double from w(ns):w(ns+1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd+1):w(nd) 1 2 none mul mul.ss wb,ws,wnd {wnd+1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none neg neg f f = f + 1 1 1 c, dc, n, ov, z neg f,wreg wreg = f + 1 1 1 c, dc, n, ov, z neg ws,wd wd = ws + 1 1 1 c, dc, n, ov, z nop nop no operation 1 1 none nopr no operation 1 1 none pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd+1) 1 2 none pop.s pop shadow registers 1 1 all push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fj256gb210 family ds39975a-page 344 ? 2010 microchip technology inc. pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto, sleep rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none reset reset software device reset 1 1 none retfie retfie return from interrupt 1 3 (2) none retlw retlw #lit10,wn return with literal in wn 1 3 (2) none return return return from subroutine 1 3 (2) none rlc rlc f f = rotate left through carry f 1 1 c, n, z rlc f,wreg wreg = rotate left through carry f 1 1 c, n, z rlc ws,wd wd = rotate left through carry ws 1 1 c, n, z rlnc rlnc f f = rotate left (no carry) f 1 1 n, z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n, z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n, z rrc rrc f f = rotate right through carry f 1 1 c, n, z rrc f,wreg wreg = rotate right through carry f 1 1 c, n, z rrc ws,wd wd = rotate right through carry ws 1 1 c, n, z rrnc rrnc f f = rotate right (no carry) f 1 1 n, z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n, z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n, z se se ws,wnd wnd = sign-extended ws 1 1 c, n, z setm setm f f = ffffh 1 1 none setm wreg wreg = ffffh 1 1 none setm ws ws = ffffh 1 1 none sl sl f f = left shift f 1 1 c, n, ov, z sl f,wreg wreg = left shift f 1 1 c, n, ov, z sl ws,wd wd = left shift ws 1 1 c, n, ov, z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n, z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n, z sub sub f f = f ? wreg 1 1 c, dc, n, ov, z sub f,wreg wreg = f ? wreg 1 1 c, dc, n, ov, z sub #lit10,wn wn = wn ? lit10 1 1 c, dc, n, ov, z sub wb,ws,wd wd = wb ? ws 1 1 c, dc, n, ov, z sub wb,#lit5,wd wd = wb ? lit5 1 1 c, dc, n, ov, z subb subb f f = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb f,wreg wreg = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb #lit10,wn wn = wn ? lit10 ? (c ) 1 1 c, dc, n, ov, z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c, dc, n, ov, z subb wb,#lit5,wd wd = wb ? lit5 ? (c ) 1 1 c, dc, n, ov, z subr subr f f = wreg ? f 1 1 c, dc, n, ov, z subr f,wreg wreg = wreg ? f 1 1 c, dc, n, ov, z subr wb,ws,wd wd = ws ? wb 1 1 c, dc, n, ov, z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c, dc, n, ov, z subbr subbr f f = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr f,wreg wreg = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr wb,ws,wd wd = ws ? wb ? (c ) 1 1 c, dc, n, ov, z subbr wb,#lit5,wd wd = lit5 ? wb ? (c ) 1 1 c, dc, n, ov, z swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2010 microchip technology inc. ds39975a-page 345 pic24fj256gb210 family tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none ulnk ulnk unlink frame pointer 1 1 none xor xor f f = f .xor. wreg 1 1 n, z xor f,wreg wreg = f .xor. wreg 1 1 n, z xor #lit10,wn wd = lit10 .xor. wd 1 1 n, z xor wb,ws,wd wd = wb .xor. ws 1 1 n, z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n, z ze ze ws,wnd wnd = zero-extend ws 1 1 c, z, n table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fj256gb210 family ds39975a-page 346 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 347 pic24fj256gb210 family 29.0 electrical characteristics this section provides an overview of the pic24fj256gb210 family electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic24fj256gb210 family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any combined analog and digital pin and mclr , with respect to v ss ......................... -0.3v to (v dd + 0.3v) voltage on any digital only pin with respect to v ss when v dd < 3.0v............................................ -0.3v to (v dd + 0.3v) voltage on any digital only pin with respect to v ss when v dd > 3.0v..................................................... -0.3v to (+5.5v) voltage on v bus pin with respect to v ss , independent of v dd or v usb ...................................................-0.3v to (+5.5v) maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (note 1) ................................................................................................................250 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (note 1) ....................................................................................................200 ma note 1: maximum allowable current is a function of device maximum power dissipation (see table 29-1). ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic24fj256gb210 family ds39975a-page 348 ? 2010 microchip technology inc. 29.1 dc characteristics figure 29-1: pic24f j256gb210 family voltage frequency graph (industrial) table 29-1: thermal operating conditions rating symbol min typ max unit pic24fj256gb210 family: operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c power dissipation (with envreg = 1 ): internal chip power dissipation: p int = v dd x (i dd ? ? i oh ) p d p int + p i / o w i/o pin power dissipation: p i / o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t jmax ? t a )/ ? ja w frequency voltage (v dd ) v bor 32 mhz 3.6v 3.6v pic24fjxxxda1 v bor 2.2v 2.2v note: v cap (nominal on-chip regulator output voltage) = 1.8v. table 29-2: thermal packaging characteristics characteristic symbol typ max unit note package thermal resistance, 12x12x1 mm tqfp ? ja 69.4 ? c/w (note 1) package thermal resistance, 10x10x1 mm tqfp ? ja 76.6 ? c/w (note 1) package thermal resistance, 9x9x0.9 mm qfn ? ja 28.0 ? c/w (note 1) package thermal resistance, 10x10x1.1 mm bga ? ja 40.2 ? c/w (note 1) note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations.
? 2010 microchip technology inc. ds39975a-page 349 pic24fj256gb210 family table 29-3: dc characteristics: temperature and voltage specifications dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ max units conditions operating voltage dc10 supply voltage v dd v bor ? 3.6 v regulator enabled v cap (2) ? 1.8v ? v regulator enabled dc12 v dr ram data retention voltage (1) 1.5 ? ? v dc16 v por v dd start voltage to ensure internal power-on reset signal vss ? ? v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms 0-3.3v in 66 ms 0-2.5v in 50 ms v bor brown-out reset voltage on v dd transition, high-to-low 2.0 2.10 2.2 v regulator enabled v lvd lvd trip voltage ? v bor + 0.10 ? v note 1: this is the limit to which the ram data can be retained, while the on-chip regulator output voltage starts following the v dd . 2: this is the on-chip regulator output voltage specification.
pic24fj256gb210 family ds39975a-page 350 ? 2010 microchip technology inc. table 29-4: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (1) max units conditions operating current (i dd ) (2) dc20d 0.8 1.3 ma -40c 3.3v (3) 1 mips dc20e 0.8 1.3 ma +25c dc20f 0.8 1.3 ma +85c dc23d 3.0 4.8 ma -40c 3.3v (3) 4 mips dc23e 3.0 4.8 ma +25c dc23f 3.0 4.8 ma +85c dc24d 12.0 18 ma -40c 3.3v (3) 16 mips dc24e 12.0 18 ma +25c dc24f 12.0 18 ma +85c dc31d 55 95 ? a-40c 3.3v (3) lprc (31 khz) dc31e 55 95 ? a +25c dc31f 135 225 ? a +85c note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: osci driven with external square wave from rail to rail. a ll i/o pins are configured as inputs and pulled to v dd . mclr =v dd ; wdt and fscm are disabled. cpu, sram, program memory and data memory are operational. no peripheral modules are operating and all of the peripheral module disable (pmd) bits are set. 3: on-chip voltage regulator enabled (envreg tied to v dd ). brown-out reset (bor) is enabled.
? 2010 microchip technology inc. ds39975a-page 351 pic24fj256gb210 family table 29-5: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (1) max units conditions idle current (i idle ) (2) dc40d 170 320 ? a-40c 3.3v (3) 1 mips dc40e 170 320 ? a+25c dc40f 220 380 ? a+85c dc43d 0.6 1.2 ma -40c 3.3v (3) 4 mips dc43e 0.6 1.2 ma +25c dc43f 0.7 1.2 ma +85c dc47d 2.3 4.8 ma -40c 3.3v (3) 16 mips dc47e 2.3 4.8 ma +25c dc47f 2.4 4.8 ma +85c dc50d 0.8 1.8 ma -40c 3.3v (3) frc (4 mips) dc50e 0.8 1.8 ma +25c dc50f 1.0 1.8 ma +85c dc51d 40.0 85 ? a-40c 3.3v (3) lprc (31 khz) dc51e 40.0 85 ? a+25c dc51f 120.0 210 ? a+85c note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with the core off; osci driven with external square wave from rail to rail. all i/o pins are configured as inputs and pulled to v dd . mclr = v dd ; wdt and fscm are disabled. no peripheral modules are operating and all of the peripheral module disable (pmd) bits are set. 3: on-chip voltage regulator enabled (envreg tied to v dd ). brown-out reset (bor) is enabled.
pic24fj256gb210 family ds39975a-page 352 ? 2010 microchip technology inc. table 29-6: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial parameter no. typical (1) max units conditions power-down current (i pd ) (2) dc60d 20.0 45 ? a-40c 3.3v (3) base power-down current (4) dc60e 20.0 45 ? a+25c dc60h 55.0 105 ? a+60c dc60f 95.0 185 ? a+85c dc61d 1.0 3.5 ? a-40c 3.3v (3) 31 khz lprc oscillator with rtcc, wdt or timer1: ? i lprc (4) dc61e 1.0 3.5 ? a+25c dc61h 1.0 3.5 ? a+60c dc61f 2.5 6.5 ? a+85c dc62d 1.5 6 ? a-40c 3.3v (3) low drive strength, 32 khz crystal with rtcc or timer1: ? i sosc ; soscsel<1:0> = 01 (4) dc62e 1.5 6 ? a+25c dc62h 1.5 6 ? a+60c dc62f 8.0 18 ? a+85c dc63d 4.0 18 ? a-40c 3.3v (3) 32 khz crystal with rtcc or timer1: ? i sosc ; soscsel<1:0> = 11 (4) dc63e 4.0 18 ? a+25c dc63h 6.5 18 ? a+60c dc63f 12.0 25 ? a+85c note 1: data in the typical column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with the device in sleep mode (all peripherals and clocks are shut down). all i/os are configured as inputs and pulled high. wdt, etc., are all switched off, pmslp bit is clear and the peripheral module disable (pmd) bits for all unused peripherals are set. 3: on-chip voltage regulator enabled (envreg tied to v dd ). brown-out reset (bor) is enabled. 4: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current.
? 2010 microchip technology inc. ds39975a-page 353 pic24fj256gb210 family table 29-7: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions v il input low voltage (3) di10 i/o pins with st buffer v ss ?0.2 v dd v di11 i/o pins with ttl buffer v ss ?0.15 v dd v di15 mclr v ss ?0.2 v dd v di16 osci (xt mode) v ss ?0.2 v dd v di17 osci (hs mode) v ss ?0.2 v dd v di18 i/o pins with i 2 c? buffer: v ss ?0.3 v dd v di19 i/o pins with smbus buffer: v ss ? 0.8 v smbus enabled v ih input high voltage (3) di20 i/o pins with st buffer: with analog functions digital only 0.8 v dd 0.8 v dd ? ? v dd 5.5 v v di21 i/o pins with ttl buffer: with analog functions digital only 0.25 v dd + 0.8 0.25 v dd + 0.8 ? ? v dd 5.5 v v di25 mclr 0.8 v dd ?v dd v di26 osci (xt mode) 0.7 v dd ?v dd v di27 osci (hs mode) 0.7 v dd ?v dd v di28 i/o pins with i 2 c? buffer: with analog functions digital only 0.7 v dd 0.7 v dd ? ? v dd 5.5 v v di29 i/o pins with smbus buffer: with analog functions digital only 2.1 2.1 v dd 5.5 v v 2.5v ? v pin ? v dd di30 i cnpu cnxx pull-up current 15 70 150 ? av dd = 3.3v, v pin = v ss di30a i cnpd cnxx pull-down current 150 350 550 ? av dd = 3.3v, v pin = v dd i il input leakage current (2) di50 i/o ports ? ? + 1 ? av ss ? v pin ? v dd , pin at high-impedance di51 analog input pins ? ? + 1 ? av ss ? v pin ? v dd , pin at high-impedance di55 mclr ??+ 1 ? av ss ?? v pin ?? v dd di56 osci/clki ? ? + 1 ? av ss ?? v pin ?? v dd , ec, xt and hs modes note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: negative current is defined as current sourced by the pin. 3: refer to table 1-3 for i/o pins buffer types.
pic24fj256gb210 family ds39975a-page 354 ? 2010 microchip technology inc. table 29-8: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions v ol output low voltage do10 i/o ports ? ? 0.4 v i ol = 6.6ma, v dd = 3.6v ??0.4vi ol = 5.0 ma, v dd = 2.2v do16 osco/clko ? ? 0.4 v i ol = 6.6 ma, v dd = 3.6v ??0.4vi ol = 5.0 ma, v dd = 2.2v v oh output high voltage do20 i/o ports 3.0 ? ? v i oh = -3.0 ma, v dd = 3.6v 2.4 ? ? v i oh = -6.0 ma, v dd = 3.6v 1.65 ? ? v i oh = -1.0 ma, v dd = 2.2v 1.4 ? ? v i oh = -3.0 ma, v dd = 2.2v do26 osco/clko 2.4 ? ? v i oh = -6.0 ma, v dd = 3.6v 1.4 ? ? v i oh = -1.0 ma, v dd = 2.2v note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 29-9: dc characteristics: program memory dc characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions program flash memory d130 e p cell endurance 10000 ? ? e/w -40 ? c to +85 ? c d131 v pr v dd for read v min ?3.6 vv min = minimum operating voltage d132b v dd for self-timed write v min ?3.6 vv min = minimum operating voltage d133a t iw self-timed word write cycle time ?20? ? s self-timed row write cycle time ?1.5?ms d133b t ie self-timed page erase time 20 ? 40 ms d134 t retd characteristic retention 20 ? ? year if no other specifications are violated d135 i ddp supply current during programming ?16?ma note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated.
? 2010 microchip technology inc. ds39975a-page 355 pic24fj256gb210 family table 29-10: internal voltag e regulator specifications 29.2 ac characteristics and timing parameters the information contained in this section defines the pic24f j256gb210 family ac characteristics and timing parameters. table 29-11: temperature and vo ltage specifications ? ac figure 29-2: load conditions for device timing specifications operating conditions: -40c < t a < +85c (unless otherwise stated) param no. symbol characteristics min typ max units comments v rgout regulator output voltage ? 1.8 ? v v bg internal band gap reference ? 1.2 ? v c efc external filter capacitor value 4.7 10 ? ? f series resistance < 3 ohm recommended; < 5 ohm required. t vreg ?10? ? svregs = 1 , vregs = 0 with wutsel<1:0> = 01 or any por or bor ? 190 ? ? s sleep wake-up with vregs = 0 and wutsel<1:0> = 11 t bg band gap reference start-up time ?1?ms ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial operating voltage v dd range as described in section 29.1 ?dc characteristics? . v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osco 15 pf for osco output load condition 1 ? for all pins except osco load condition 2 ? for osco
pic24fj256gb210 family ds39975a-page 356 ? 2010 microchip technology inc. table 29-12: capacitiv e loading requirements on output pins figure 29-3: external clock timing param no. symbol characteristic min typ (1) max units conditions do50 c osco osco/clko pin ? ? 15 pf in xt and hs modes when external clock is used to drive osci do56 c io all i/o pins and osco ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. osci clko q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31 q1 q2 q3 q4 q2 q3
? 2010 microchip technology inc. ds39975a-page 357 pic24fj256gb210 family table 29-13: external clo ck timing requirements ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions os10 f osc external clki frequency (external clocks allowed only in ec mode) dc 4 ? ? 32 48 mhz mhz ec ecpll oscillator frequency 3.5 4 10 10 31 ? ? ? ? ? 10 8 32 32 33 mhz mhz mhz mhz khz xt xtpll hs hspll sosc os20 t osc t osc = 1/f osc ? ? ? ? see parameter os10 for f osc value os25 t cy instruction cycle time (2) 62.5 ? dc ns os30 tosl, to sh external clock in (osci) high or low time 0.45 x t osc ??nsec os31 tosr, to sf external clock in (osci) rise or fall time ? ? 20 ns ec os40 tckr clko rise time (3) ? 6 10 ns os41 tckf clko fall time (3) ? 6 10 ns note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osci/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osco pin. clko is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ). table 29-14: pll clock ti ming specifications (v dd = 2.2v to 3.6v) ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range (2) 4 ? 48 mhz ecpll mode 4 ? 32 mhz hspll mode 4 ? 8 mhz xtpll mode os51 f sys pll output frequency range 95.76 ? 96.24 mhz os52 t lock pll start-up time (lock time) ??200 ? s os53 d clk clko stability (jitter) -0.25 ? 0.25 % note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested.
pic24fj256gb210 family ds39975a-page 358 ? 2010 microchip technology inc. table 29-15: internal rc accuracy ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ?? +85c for industrial param no. characteristic min typ max units conditions f20 frc accuracy @ 8mhz (1,2) -1 0.15 1 % -40c ? t a ?? +85c 2.2v ? v dd ?? 3.6v f21 lprc @ 31 khz -20 ? 20 % -40c ? t a ?? +85c v cap (on-chip regulator output voltage) = 1.8v note 1: frequency calibrated at 25c and 3.3v. osctun bits can be used to compensate for temperature drift. 2: to achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the pcb) must be kept to a minimum. table 29-16: rc oscillator start-up time ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. characteristic min typ max units conditions t frc ?15? ? s t lprc ?50? ? s table 29-17: reset and brown -out reset requirements ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ max units conditions sy10 t mcl mclr pulse width (low) 2 ? ? ? s sy12 t por power-on reset delay ? 2 ? ? s sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset ? ? 100 ns sy25 t bor brown-out reset pulse width 1 ? ? ? sv dd ?? v bor t rst internal state reset time ? 50 ? ? s
? 2010 microchip technology inc. ds39975a-page 359 pic24fj256gb210 family figure 29-4: clko and i/o ti ming characteristics note: refer to figure 29-2 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 29-18: clko and i/ o timing requirements ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ (1) max units conditions do31 t io r port output rise time ? 10 25 ns do32 t io f port output fall time ? 10 25 ns di35 t inp intx pin high or low time (input) 20 ? ? ns di40 t rbp cnx high or low time (input) 2??t cy note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated.
pic24fj256gb210 family ds39975a-page 360 ? 2010 microchip technology inc. table 29-19: adc mo dule specifications ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.2 ?lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss ? 0.3 ? v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 1.7 ? av dd v ad06 v refl reference voltage low av ss ?av dd ? 1.7 v ad07 v ref absolute reference voltage av ss ? 0.3 ? av dd + 0.3 v analog input ad10 v inh -v inl full-scale input span v refl ?v refh v (note 2) ad11 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ad12 v inl absolute v inl input voltage av ss ? 0.3 av dd /2 v ad13 leakage current ? 1.0 610 na v inl = av ss = v refl = 0v, av dd = v refh = 3v, source impedance = 2.5 k ? ad17 r in recommended impedance of analog voltage source ? ? 2.5k ? 10-bit adc accuracy ad20b nr resolution ? 10 ? bits ad21b inl integral nonlinearity ? 1 <2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad22b dnl differential nonlinearity ? 0.5 <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad23b g err gain error ? 1 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad24b e off offset error ? 1 2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad25b monotonicity (1) ? ? ? ? guaranteed note 1: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 2: measurements taken with external v ref + and v ref - used as the adc voltage reference.
? 2010 microchip technology inc. ds39975a-page 361 pic24fj256gb210 family table 29-20: adc conversion timing requirements (1) ac characteristics standard operating conditions: 2.2v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad adc clock period 75 ? ? ns t cy = 75 ns, ad1con3 in default state ad51 t rc adc internal rc oscillator period ? 250 ? ns conversion rate ad55 t conv conversion time ? 12 ? t ad ad56 f cnv throughput rate ? ? 500 ksps av dd > 2.7v ad57 t samp sample time ? 1 ? t ad clock parameters ad61 t pss sample start delay from setting sample bit (samp) 2?3t ad note 1: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures.
pic24fj256gb210 family ds39975a-page 362 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 363 pic24fj256gb210 family 30.0 packaging information 30.1 package marking information 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic24fj256 gb206-i/ 1020017 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn pt 3 e example pic24fj256gb 210-i/pt 1020017 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 121-bga (10x10x1.1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic24fj256gb 210-i/bg 1020017 3 e xxxxxxxxxxx 64-lead qfn (9x9x0.9 mm) xxxxxxxxxxx xxxxxxxxxxx yywwnnn pic24fj256 example gb206-i/mr 1010017 3 e
pic24fj256gb210 family ds39975a-page 364 ? 2010 microchip technology inc. 30.2 package details the following sections give the technical details of the packages.

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? 2010 microchip technology inc. ds39975a-page 367 pic24fj256gb210 family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic24fj256gb210 family ds39975a-page 368 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010 microchip technology inc. ds39975a-page 369 pic24fj256gb210 family

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? 2010 microchip technology inc. ds39975a-page 371 pic24fj256gb210 family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic24fj256gb210 family ds39975a-page 372 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010 microchip technology inc. ds39975a-page 373 pic24fj256gb210 family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic24fj256gb210 family ds39975a-page 374 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 375 pic24fj256gb210 family appendix a: revision history revision a (may 2010) original data sheet for the pic24fj256gb210 family of devices.
pic24fj256gb210 family ds39975a-page 376 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 377 pic24fj256gb210 family index a a/d conversion 10-bit high-speed a/d converter............................. 301 a/d converter ................................................................... 301 analog input model ................................................... 309 transfer function...................................................... 309 ac characteristics a/d specifications..................................................... 360 adc conversion timing requirements .................... 361 capacitive loading on output pin ............................ 356 clko and i/o timing................................................ 359 external clock timing ............................................... 357 internal rc accuracy ................................................ 358 load conditions and requirements for specifications.................................................... 355 pll clock timing specifications............................... 357 rc oscillator start-up time ...................................... 358 reset and brown-out reset requirements .............. 358 timing parameters.................................................... 355 alternate interrupt vector table (aivt) .............................. 91 assembler mpasm assembler................................................... 336 b block diagram crc .......................................................................... 293 block diagrams 10-bit high-speed a/d converter............................. 302 16-bit asynchronous timer3 and timer5 ................. 187 16-bit synchronous timer2 and timer4 ................... 187 16-bit timer1 module................................................ 183 32-bit timer2/3 and timer4/5 ................................... 186 96 mhz pll .............................................................. 145 accessing program space using table operations .......................................................... 74 addressing for table registers................................... 79 bdt mapping for endpoint buffering modes ............ 239 call stack frame...................................................... 72 comparator voltage reference ................................ 317 cpu programmer?s model .......................................... 39 crc shift engine detail............................................ 293 ctmu connections and internal configuration for capacitance measurement.......................... 319 ctmu typical connections and internal configuration for pulse delay generation ........ 320 ctmu typical connections and internal configuration for time measurement ............... 320 data access from program space address generation .......................................................... 73 eds address generation for read operations .......... 69 eds address generation for write operations .......... 70 extended data space ................................................. 68 i 2 c module ................................................................ 218 individual comparator configurations, cref = 0 .......................................................... 312 individual comparator configurations, cref = 1 and cvrefp = 0 ............................. 313 individual comparator configurations, cref = 1 and cvrefp = 1 ............................. 313 input capture ............................................................ 191 on-chip regulator connections ............................... 330 output compare (16-bit mode)................................. 196 output compare (double-buffered, 16-bit pwm mode) ........................................... 198 pic24f cpu core ...................................................... 38 pic24fj256gb210 family (general)......................... 19 psv operation (higher word) .................................... 76 psv operation (lower word)..................................... 76 reset system ............................................................. 85 rtcc........................................................................ 281 shared i/o port structure ......................................... 151 spi master, frame master connection .................... 214 spi master, frame slave connection ...................... 214 spi master/slave connection (enhanced buffer modes) ................................................... 213 spi master/slave connection (standard mode)....... 213 spi slave, frame master connection ...................... 214 spi slave, frame slave connection ........................ 214 spix module (enhanced mode)................................ 207 spix module (standard mode) ................................. 206 system clock............................................................ 137 triple comparator module........................................ 311 uart (simplified)..................................................... 225 usb otg device mode power modes .................... 235 usb otg dual power example............................... 236 usb otg external pull-up for full-speed device mode..................................................... 235 usb otg interface example ................................... 237 usb otg interrupt funnel ....................................... 243 usb otg module..................................................... 234 usb otg self-power only ...................................... 235 watchdog timer (wdt)............................................ 331 c c compilers mplab c18 .............................................................. 336 charge time measurement unit (ctmu)......................... 319 key features ............................................................ 319 charge time measurement unit. see ctmu. code examples basic sequence for clock switching in assembly.... 144 configuring uart1 i/o input/output functions (pps) ............................................... 162 eds read code from program memory in assembly ........................................................ 77 eds read code in assembly..................................... 69 eds write code in assembly..................................... 70 erasing a program memory block (assembly) ........... 82 i/o port write/read in ?c? ......................................... 157 i/o port write/read in assembly.............................. 157 initiating a programming sequence ........................... 83 pwrsav instruction syntax .................................... 149 setting the rtcwren bit........................................ 282 single-word flash programming ............................... 84 single-word flash programming (?c? language)....... 84 code protection ................................................................ 332 code segment protection ........................................ 332 configuration options....................................... 333 configuration register protection............................. 333 comparator voltage reference ........................................ 317 configuring ............................................................... 317 configuration bits ............................................................. 323 core features..................................................................... 15
pic24fj256gb210 family ds39975a-page 378 ? 2010 microchip technology inc. cpu arithmetic logic unit (alu)......................................... 41 control registers ........................................................ 40 core registers ............................................................ 38 programmer?s model................................................... 37 crc 32-bit programmable cycl ic redundancy check ..... 293 polynomials............................................................... 294 setup examples for 16 and 32-bit polynomials ........ 294 user interface ........................................................... 294 ctmu measuring capacitance ............................................ 319 measuring time ........................................................ 320 pulse generation and delay ..................................... 320 customer change notification service ............................. 382 customer notification service........................................... 382 customer support ............................................................. 382 d data memory address space............................................................ 45 extended data space (eds) ...................................... 68 memory map ............................................................... 46 near data space ........................................................ 47 sfr space.................................................................. 47 software stack............................................................ 72 space organization, alignment .................................. 47 dc characteristics i/o pin input specifications ....................................... 353 i/o pin output specifications .................................... 354 idle current ............................................................... 351 operating current ..................................................... 350 program memory ...................................................... 354 temperature and voltage specifications .................. 349 thermal conditions ................................................... 348 voltage regulator specifications .............................. 355 development support ....................................................... 335 device features 100/121--pin ............................................................... 18 64-pin.......................................................................... 17 doze mode........................................................................ 150 e electrical characteristics absolute maximum ratings ...................................... 347 v/f graph ................................................................. 348 enhanced parallel master port. see epmp...................... 269 envreg pin..................................................................... 330 epmp ................................................................................ 269 altpmp setting ....................................................... 269 key features............................................................. 269 master port pins ....................................................... 270 equations 16-bit, 32-bit crc polynomials ................................ 294 a/d conversion clock period ................................... 308 baud rate reload calculation .................................. 219 calculating the pwm period ..................................... 198 calculation for maximum pwm resolution............... 199 estimating usb transceiver current consumption..................................................... 238 relationship between device and spi clock speed...................................................... 215 rtcc calibration ...................................................... 290 uart baud rate with brgh = 0 ............................. 226 uart baud rate with brgh = 1 ............................. 226 errata .................................................................................. 14 extended data space (eds) ............................................ 269 f flash configuration words ......................................... 44, 323 flash program memory ...................................................... 79 enhanced icsp operation ......................................... 80 jtag operation.......................................................... 80 programming algorithm .............................................. 82 rtsp operation ......................................................... 80 single-word programming ......................................... 84 table instructions ....................................................... 79 i i/o ports analog port pins configuration................................. 152 analog/digital function of an i/o pin........................ 152 input change notification ......................................... 157 open-drain configuration......................................... 152 parallel (pio) ............................................................ 151 peripheral pin select ................................................ 158 pull-ups and pull-downs........................................... 157 selectable input sources.......................................... 159 write/read timing .................................................... 152 i 2 c clock rates .............................................................. 219 reserved addresses ................................................ 219 setting baud rate as bus master............................. 219 slave address masking ............................................ 219 idle mode .......................................................................... 150 input capture 32-bit mode (cascaded)........................................... 192 operations ................................................................ 192 synchronous and trigger modes.............................. 191 input capture with dedicated timers ............................... 191 input voltage levels for port or pin tolerated description input....................................... 152 instruction set opcode symbols ...................................................... 340 overview................................................................... 341 summary .................................................................. 339 instruction-based power-saving modes................... 149, 150 interfacing program and data spaces................................ 72 inter-integrated circuit. see i 2 c. ...................................... 217 internet address ............................................................... 382 interrupt vector table (ivt) ................................................ 91 interrupts control and status registers...................................... 94 implemented vectors.................................................. 93 reset sequence ......................................................... 91 setup and service procedures ................................. 135 trap vector details ..................................................... 92 vector table ............................................................... 92 j jtag interface.................................................................. 333 k key features .................................................................... 323
? 2010 microchip technology inc. ds39975a-page 379 pic24fj256gb210 family m memory organization.......................................................... 43 microchip internet web site .............................................. 382 mplab asm30 assembler, linker, librarian ................... 336 mplab integrated development environment software.................................................................... 335 mplab pm3 device programmer .................................... 338 mplab real ice in-circuit emulator system................. 337 mplink object linker/mplib object librarian ................ 336 n near data space ................................................................ 47 o oscillator configuration 96 mhz pll .............................................................. 144 clock selection ......................................................... 138 clock switching......................................................... 143 sequence.......................................................... 143 cpu clocking scheme ............................................. 138 initial configuration on por ..................................... 138 usb operations ........................................................ 146 output compare 32-bit mode (cascaded) ........................................... 195 synchronous and trigger modes.............................. 195 output compare with dedicated timers........................... 195 p packaging ......................................................................... 363 details ....................................................................... 364 marking ..................................................................... 363 peripheral enable bits ...................................................... 150 peripheral module disable bits ......................................... 150 peripheral pin select (pps) .............................................. 158 available peripherals and pins ................................. 158 configuration control ................................................ 161 considerations for use ............................................. 162 input mapping ........................................................... 158 mapping exceptions.................................................. 161 output mapping ........................................................ 160 peripheral priority ..................................................... 158 registers................................................................... 163 pin descriptions 100-pin devices............................................................ 8 121-pin (bga) devices............................................... 11 64-pin devices.............................................................. 6 pin diagrams 100-pin tqfp ............................................................... 7 121-pin bga ............................................................... 10 64-pin tqfp/qfn ........................................................ 5 pinout descriptions ............................................................. 20 por and on-chip voltage regulator................................ 330 power-saving features .................................................... 149 clock frequency and clock switching...................... 149 instruction-based modes .......................................... 149 power-up requirements ................................................... 330 product identification system ........................................... 384 program memory access using table instructions................................. 74 address construction.................................................. 72 address space............................................................ 43 flash configuration words ......................................... 44 memory maps ............................................................. 43 organization................................................................ 44 reading from program memory using eds.............. 75 program verification ......................................................... 332 pulse-width modulation (pwm) mode.............................. 197 pulse-width modulation. see pwm. pwm duty cycle and period.............................................. 198 r reader response............................................................. 383 reference clock output ................................................... 147 register maps a/d converter............................................................. 59 ancfg ....................................................................... 62 ansel........................................................................ 62 comparators............................................................... 64 cpu core ................................................................... 48 crc............................................................................ 64 ctmu ......................................................................... 60 i 2 c?........................................................................... 54 icn ............................................................................. 49 input capture.............................................................. 52 interrupt controller...................................................... 50 nvm............................................................................ 67 output compare ......................................................... 53 pad configuration....................................................... 58 peripheral pin select .................................................. 65 pmd............................................................................ 67 porta ....................................................................... 56 portb ....................................................................... 56 portc ....................................................................... 57 portd ....................................................................... 57 porte ....................................................................... 57 portf ....................................................................... 58 portg....................................................................... 58 rtcc.......................................................................... 63 spi.............................................................................. 56 system........................................................................ 67 timers......................................................................... 51 uart.......................................................................... 55 usb otg ................................................................... 61 registers ad1chs (a/d input select)...................................... 306 ad1con1 (a/d control 1)........................................ 303 ad1con2 (a/d control 2)........................................ 304 ad1con3 (a/d control 3)........................................ 305 ad1cssh (a/d input scan select, high)................. 308 ad1cssl (a/d input scan select, low) .................. 307 alcfgrpt (alarm configuration) ........................... 285 alminsec (alarm minutes and seconds value)..... 289 almthdy (alarm month and day value) ................ 288 alwdhr (alarm weekday and hours value) ......... 289 ancfg (a/d band gap reference configuration) ................................................... 307 ansa (porta analog function selection) ............. 153 ansb (portb analog function selection) ............. 154 ansc (portc analog function selection) ............. 154 ansd (portd analog function selection) ............. 155 anse (porte analog function selection) ............. 155 ansf (portf analog function selection).............. 156 ansg (portg analog function selection) ............ 156 bdnstat prototype (buffer descriptor n status, cpu mode) ............................................................... 242 bdnstat prototype (buffer descriptor n status, usb mode)........................................... 241 clkdiv (clock divider) ............................................ 141 cmstat (comparator status) ................................. 315
pic24fj256gb210 family ds39975a-page 380 ? 2010 microchip technology inc. cmxcon (comparator x control, comparators 1-3)............................................. 314 corcon (cpu core control).............................. 41, 96 crccon1 (crc control 1) ..................................... 296 crccon2 (crc control 2) ..................................... 297 crcdath (crc data high) .................................... 298 crcdatl (crc data low)...................................... 298 crcwdath (crc shift high) ................................. 299 crcwdatl (crc shift low)................................... 299 crcxorh (crc xor high) ................................... 298 crcxorl (crc xor polynomial, low byte) ......... 297 ctmucon (ctmu control) ..................................... 321 ctmuicon (ctmu current control) ....................... 322 cvrcon (comparator voltage reference control)............................................ 318 cw1 (flash configuration word 1)........................... 324 cw2 (flash configuration word 2)........................... 326 cw3 (flash configuration word 3)........................... 327 cw4 (flash configuration word 4)........................... 328 devid (device id) .................................................... 329 devrev (device revision) ...................................... 329 i2cxcon (i2cx control) ........................................... 220 i2cxmsk (i2cx slave mode address mask) ............ 224 i2cxstat (i2cx status) ........................................... 222 icxcon1 (input capture x control 1) ....................... 193 icxcon2 (input capture x control 2) ....................... 194 iec0 (interrupt enable control 0) ............................. 106 iec1 (interrupt enable control 1) ............................. 107 iec2 (interrupt enable control 2) ............................. 109 iec3 (interrupt enable control 3) ............................. 110 iec4 (interrupt enable control 4) ............................. 111 iec5 (interrupt enable control 5) ............................. 112 ifs0 (interrupt flag status 0) ..................................... 99 ifs1 (interrupt flag status 1) ................................... 100 ifs2 (interrupt flag status 2) ................................... 101 ifs3 (interrupt flag status 3) ................................... 103 ifs4 (interrupt flag status 4) ................................... 104 ifs5 (interrupt flag status 5) ................................... 105 intcon1 (interrupt control 1).................................... 97 intcon2 (interrupt control 2).................................... 98 inttreg (interrupt controller test) ......................... 134 ipc0 (interrupt priority control 0) ............................. 113 ipc1 (interrupt priority control 1) ............................. 114 ipc10 (interrupt priority control 10) ......................... 123 ipc11 (interrupt priority control 11) ......................... 124 ipc12 (interrupt priority control 12) ......................... 125 ipc13 (interrupt priority control 13) ......................... 126 ipc15 (interrupt priority control 15) ......................... 127 ipc16 (interrupt priority control 16) ......................... 128 ipc18 (interrupt priority control 18) ......................... 129 ipc19 (interrupt priority control 19) ......................... 129 ipc2 (interrupt priority control 2) ............................. 115 ipc20 (interrupt priority control 20) ......................... 130 ipc21 (interrupt priority control 21) ......................... 131 ipc22 (interrupt priority control 22) ......................... 132 ipc23 (interrupt priority control 23) ......................... 133 ipc3 (interrupt priority control 3) ............................. 116 ipc4 (interrupt priority control 4) ............................. 117 ipc5 (interrupt priority control 5) ............................. 118 ipc6 (interrupt priority control 6) ............................. 119 ipc7 (interrupt priority control 7) ............................. 120 ipc8 (interrupt priority control 8) ............................. 121 ipc9 (interrupt priority control 9) ............................. 122 minsec (rtcc minutes and seconds value) ......... 287 mthdy (rtcc month and day value) .................... 286 nvmcon (flash memory control) ............................. 81 ocxcon1 (output compare x control 1) ................ 200 ocxcon2 (output compare x control 2) ................ 202 osccon (oscillator control) ................................... 139 osctun (frc oscillator tune)............................... 142 padcfg1 (pad configuration control) ............ 279, 284 pmcon1 (epmp control 1) ..................................... 271 pmcon2 (epmp control 2) ..................................... 272 pmcon3 (epmp control 3) ..................................... 273 pmcon4 (epmp control 4) ..................................... 274 pmcsxbs (chip select x base address)................. 276 pmcsxcf (chip select x configuration).................. 275 pmcsxmd (chip select x mode) ............................. 277 pmstat (epmp status, slave mode) ..................... 278 rcfgcal (rtcc calibration and configuration) ................................................... 283 rcon (reset control)................................................ 86 refocon (reference oscillator control) ............... 148 rpinrn (pps input) ......................................... 163?173 rporn (pps output) ....................................... 174?181 spixcon1 (spix control 1)...................................... 210 spixcon2 (spix control 2)...................................... 212 spixstat (spix status and control) ....................... 208 sr (alu status) ............................................... 40, 95 t1con (timer1 control) .......................................... 184 txcon (timer2 and timer4 control) ....................... 188 tycon (timer3 and timer5 control) ....................... 189 u1addr (usb address) .......................................... 256 u1cnfg1 (usb configuration 1)............................. 257 u1cnfg2 (usb configuration 2)............................. 258 u1con (usb control, device mode)....................... 254 u1con (usb control, host mode) .......................... 255 u1eie (usb error interrupt enable) ......................... 265 u1eir (usb error interrupt status).......................... 264 u1epn (usb endpoint n control)............................. 266 u1ie (usb interrupt enable) .................................... 263 u1ir (usb interrupt status, device mode) .............. 261 u1ir (usb interrupt status, host mode).................. 262 u1otgcon (usb otg control) ............................. 251 u1otgie (usb otg interrupt enable, host mode) ....................................................... 260 u1otgir (usb otg interrupt status, host mode) ....................................................... 259 u1otgstat (usb otg status, host mode) .......... 250 u1pwmcon usb (v bus pwm generator control)............................................ 267 u1pwrc (usb power control)................................ 252 u1sof (usb otg start-of-token threshold, host mode) ....................................................... 257 u1stat (usb status) .............................................. 253 u1tok (usb token, host mode)............................. 256 uxmode (uartx mode).......................................... 228 uxsta (uartx status and control)......................... 230 wkdyhr (rtcc weekday and hours value)......... 287 year (rtcc year value)........................................ 286 resets bor (brown-out reset).............................................. 85 clock source selection............................................... 88 cm (configuration mismatch reset)........................... 85 delay times................................................................ 89 device times .............................................................. 88 iopuwr (illegal opcode reset) ................................ 85 mclr (pin reset)....................................................... 85 por (power-on reset)............................................... 85 rcon flags operation............................................... 87
? 2010 microchip technology inc. ds39975a-page 381 pic24fj256gb210 family sfr states.................................................................. 88 swr (reset instruction)........................................... 85 trapr (trap conflict reset)...................................... 85 uwr (uninitialized w register reset) ....................... 85 wdt (watchdog timer reset).................................... 85 revision history ................................................................ 375 rtcc alarm configuration .................................................. 290 calibration................................................................. 290 key features............................................................. 281 register mapping...................................................... 282 s selective peripheral power control .................................. 150 serial peripheral interface (spi) ....................................... 205 serial peripheral interface. see spi. sfr space.......................................................................... 47 sleep mode ....................................................................... 149 software simulator (mplab sim)..................................... 337 software stack.................................................................... 72 special features ................................................................. 16 spi .................................................................................... 205 t timer1 ............................................................................... 183 timer2/3 and timer4/5...................................................... 185 timing diagrams clko and i/o timing................................................ 359 external clock........................................................... 356 triple comparator ............................................................. 311 triple comparator module ................................................ 311 u uart ................................................................................ 225 baud rate generator (brg)..................................... 226 irda support ............................................................. 227 operation of uxcts and uxrts pins ...................... 227 receiving in 8-bit or 9-bit data mode....................... 227 transmitting break and sync sequence ............................... 227 in 8-bit data mode ............................................ 227 transmitting in 9-bit data mode ............................... 227 universal asynchronous receiver transmitter. see uart. universal serial bus buffer descriptors assignment in different buffering modes ......... 240 interrupts and usb transactions ...................................... 244 universal serial bus. see usb otg. usb on-the-go (otg) ...................................................... 16 usb otg ......................................................................... 233 buffer descriptors and bdt...................................... 239 device mode operation............................................ 244 dma interface........................................................... 240 hardware calculating transceiver power requirements ............ 237 hardware configuration............................................ 235 device mode..................................................... 235 external interface ............................................. 237 host and otg modes....................................... 236 v bus voltage generation ................................. 237 host mode operation ............................................... 245 interrupts .................................................................. 243 operation.................................................................. 247 registers .................................................................. 249 v bus voltage generation ......................................... 237 v voltage regulator (on-chip) ............................................ 330 and bor................................................................... 330 low-voltage detection ............................................. 330 standby mode .......................................................... 330 w watchdog timer (wdt).................................................... 331 control register........................................................ 331 windowed operation ................................................ 331 www address ................................................................. 382 www, on-line support ................... .................................. 14
pic24fj256gb210 family ds39975a-page 382 ? 2010 microchip technology inc. notes:
? 2010 microchip technology inc. ds39975a-page 383 pic24fj256gb210 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic24fj256gb210 family ds39975a-page 384 ? 2010 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39975a pic24fj256gb210 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2010 microchip technology inc. ds39975a-page 385 pic24fj256gb210 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture 24 = 16-bit modified harvard without dsp flash memory family fj = flash program memory product group gb2 = general purpose microcontrollers with usb on-the-go pin count 06 = 64-pin 10 = 100-pin (tqfp)/121-pin (bga) temperature range i = -40 ? c to +85 ? c (industrial) package pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pt = 64-lead, tqfp (thin quad flatpack) mr = 64-lead (9x9x0.9 mm) qfn (quad flatpack, no lead) bg = 121-pin bga package pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample examples: a) pic24fj128gb206-i/pt: pic24f device with usb on-the-go, 128-kb program memory, 96-kb data memory, 64-pin, industrial temp., tqfp package. b) pic24fj256gb210-i/pt: pic24f device with usb on-the-go, 256-kb program memory, 96-kb data memory, 100-pin, industrial temp., tqfp package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern pic 24 fj 256 gb2 1 0 t - i / pt - xxx tape and reel flag (if applicable)
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